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Message-ID: <CAFBinCAwcdfaqf-23rj1xOMK9R7skPZKM2LrQLq92VwiMDOy_w@mail.gmail.com>
Date: Thu, 25 Dec 2025 00:34:32 +0100
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: xianwei.zhao@...ogic.com
Cc: Philipp Zabel <p.zabel@...gutronix.de>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Neil Armstrong <neil.armstrong@...aro.org>, Kevin Hilman <khilman@...libre.com>, 
	Jerome Brunet <jbrunet@...libre.com>, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-amlogic@...ts.infradead.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 4/4] arm64: dts: amlogic: Add S7D Reset Controller

On Tue, Dec 23, 2025 at 6:37 AM Xianwei Zhao via B4 Relay
<devnull+xianwei.zhao.amlogic.com@...nel.org> wrote:
[...]
> +#define RESET_BRG_A55_PIPE0            166
For S7 (without D suffix) this is called RESET_BRG_A53_PIPE0 - which
one is correct (looking at amlogic-s7.dtsi and amlogic-s7d.dtsi
possibly A55 is correct)?
unrelated side-note while I was checking amlogic-s7.dtsi and
amlogic-s7d.dtsi: why do we have D/I and L2 caches defined for one but
not the other?

[...]
> +#define RESET_BRG_NIC_EMMC             183
> +/*                                     164     */
this needs to state 184

On a related side-note: while reviewing this patch I'm wondering how
S7 differs from S7D.
Is S7 a cut-down version of the S7D SoC (e.g. some - possibly faulty -
IP blocks fused off), is S7D a slightly updated version (like rev 2.0)
of S7, ...?
What I'm missing is a "big picture" (for older SoCs we typically had
some SBC vendor publish a datasheet - for these newer SoCs there's no
public datasheets).

That said, I think the approach chosen for the reset controller (copy
& paste, except 13 reset lines) is fine because there seem to be
actual differences in the reset lines. For other
drivers/implementations this approach would likely get very hard to
review/maintain (e.g. if we end up with a 3000 line driver and there's
only 250 lines difference between the two SoCs).


Best regards,
Martin

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