linux-kernel - Re: [PATCH v4 6/9] riscv: dts: thead: add DPU and HDMI device tree nodes

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Message-Id: <8A7BC047-96F9-4067-976F-282FA2AE8393@gmail.com>
Date: Thu, 25 Dec 2025 17:46:26 +0800
From: "Han Gao (Revy)" <rabenda.cn@...il.com>
To: Icenowy Zheng <zhengxingda@...as.ac.cn>
Cc: "Han Gao (Revy)" <rabenda.cn@...il.com>,
 Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
 Maxime Ripard <mripard@...nel.org>,
 Thomas Zimmermann <tzimmermann@...e.de>,
 David Airlie <airlied@...il.com>,
 Simona Vetter <simona@...ll.ch>,
 Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>,
 Drew Fustini <fustini@...nel.org>,
 Guo Ren <guoren@...nel.org>,
 Fu Wei <wefu@...hat.com>,
 Philipp Zabel <p.zabel@...gutronix.de>,
 Heiko Stuebner <heiko@...ech.de>,
 Andrzej Hajda <andrzej.hajda@...el.com>,
 Neil Armstrong <neil.armstrong@...aro.org>,
 Robert Foss <rfoss@...nel.org>,
 Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
 Jonas Karlman <jonas@...boo.se>,
 Jernej Skrabec <jernej.skrabec@...il.com>,
 Michal Wilczynski <m.wilczynski@...sung.com>,
 Yao Zi <ziyao@...root.org>,
 dri-devel@...ts.freedesktop.org,
 devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org,
 linux-riscv@...ts.infradead.org,
 Icenowy Zheng <uwu@...nowy.me>
Subject: Re: [PATCH v4 6/9] riscv: dts: thead: add DPU and HDMI device tree
 nodes



> On Dec 25, 2025, at 00:12, Icenowy Zheng <zhengxingda@...as.ac.cn> wrote:
> 
> From: Icenowy Zheng <uwu@...nowy.me>
> 
> T-Head TH1520 SoC contains a Verisilicon DC8200 display controller
> (called DPU in manual) and a Synopsys DesignWare HDMI TX controller.
> 
> Add device tree nodes to them.
> 
> Signed-off-by: Icenowy Zheng <uwu@...nowy.me>
> Signed-off-by: Icenowy Zheng <zhengxingda@...as.ac.cn>
> ---
> No changes in v4.
> 
> Changes in v3:
> - Adapting to the changed binding.
> 
> No changes in v2.
> 
> arch/riscv/boot/dts/thead/th1520.dtsi | 70 +++++++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index bd5d33840884e..5c0a7072f253a 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -585,6 +585,76 @@ clk_vo: clock-controller@...f528050 {
> #clock-cells = <1>;
> };
> 
> + hdmi: hdmi@...f540000 {
> + compatible = "thead,th1520-dw-hdmi";
> + reg = <0xff 0xef540000 0x0 0x40000>;
> + reg-io-width = <4>;
> + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_vo CLK_HDMI_PCLK>,
> + <&clk_vo CLK_HDMI_SFR>,
> + <&clk_vo CLK_HDMI_CEC>,
> + <&clk_vo CLK_HDMI_PIXCLK>;
> + clock-names = "iahb", "isfr", "cec", "pix";
> + resets = <&rst TH1520_RESET_ID_HDMI>,
> + <&rst TH1520_RESET_ID_HDMI_APB>;
> + reset-names = "main", "apb";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + hdmi_in: endpoint {
> + remote-endpoint = <&dpu_out_dp1>;
> + };
> + };
> +
> + hdmi_out_port: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> + dpu: display@...f600000 {
> + compatible = "thead,th1520-dc8200", "verisilicon,dc";
> + reg = <0xff 0xef600000 0x0 0x100000>;
> + interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_vo CLK_DPU_CCLK>,
> + <&clk_vo CLK_DPU_ACLK>,
> + <&clk_vo CLK_DPU_HCLK>,
> + <&clk_vo CLK_DPU_PIXELCLK0>,
> + <&clk_vo CLK_DPU_PIXELCLK1>;
> + clock-names = "core", "axi", "ahb", "pix0", "pix1";
> + resets = <&rst TH1520_RESET_ID_DPU_CORE>,
> + <&rst TH1520_RESET_ID_DPU_AXI>,
> + <&rst TH1520_RESET_ID_DPU_AHB>;
> + reset-names = "core", "axi", "ahb";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dpu_port0: port@0 {
> + reg = <0>;
> + };
> +
> + dpu_port1: port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dpu_out_dp1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&hdmi_in>;
> + };
> + };
> + };
> + };
> +
> dmac0: dma-controller@...fc00000 {
> compatible = "snps,axi-dma-1.01a";
> reg = <0xff 0xefc00000 0x0 0x1000>;
> -- 
> 2.52.0
> 
Tested-by: Han Gao <gaohan@...as.ac.cn>