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Message-Id: <20251225-knp-dts-misc-v2-1-a8a8a31fd528@oss.qualcomm.com>
Date: Thu, 25 Dec 2025 19:06:43 -0800
From: Jingyi Wang <jingyi.wang@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: aiqun.yu@....qualcomm.com, tingwei.zhang@....qualcomm.com,
trilok.soni@....qualcomm.com, yijie.yang@....qualcomm.com,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Jingyi Wang <jingyi.wang@....qualcomm.com>,
Jie Gan <jie.gan@....qualcomm.com>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH v2 1/2] arm64: dts: qcom: kaanapali: add coresight nodes
From: Jie Gan <jie.gan@....qualcomm.com>
Add CoreSight nodes to enable trace paths such as TPDM->ETF and STM->ETF.
These devices are part of the AOSS, CDSP, QDSS, modem and some small
subsystems, such as DCC, GCC, ipcc and so on.
Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@....qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1160 +++++++++++++++++++++++++++++++
1 file changed, 1160 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 51f8b3e0749c..0e63140248aa 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -1080,6 +1080,1114 @@ card-detect-pins {
};
};
+ stm@...02000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x0 0x10002000 0x0 0x1000>,
+ <0x0 0x16280000 0x0 0x180000>;
+ reg-names = "stm-base",
+ "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel_in0_in7>;
+ };
+ };
+ };
+ };
+
+ tpdm@...03000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10003000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_dcc_out: endpoint {
+ remote-endpoint = <&tpda_qdss_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@...04000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10004000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_qdss_in0: endpoint {
+ remote-endpoint = <&tpdm_dcc_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_qdss_in1: endpoint {
+ remote-endpoint = <&tpdm_spdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_qdss_out: endpoint {
+ remote-endpoint = <&funnel_in0_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@...0f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1000f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_spdm_out: endpoint {
+ remote-endpoint = <&tpda_qdss_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@...41000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10041000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ funnel_in0_in0: endpoint {
+ remote-endpoint = <&tn_ag_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ funnel_in0_in6: endpoint {
+ remote-endpoint = <&tpda_qdss_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ funnel_in0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_in0_out: endpoint {
+ remote-endpoint = <&funnel_aoss_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@...00000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11000000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_modem0_out: endpoint {
+ remote-endpoint = <&tpda_modem_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@...04000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x11004000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_modem_in0: endpoint {
+ remote-endpoint = <&tpdm_modem0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_modem_in1: endpoint {
+ remote-endpoint = <&tpdm_modem1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_modem_in2: endpoint {
+ remote-endpoint = <&tpdm_modem2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_modem_out: endpoint {
+ remote-endpoint = <&funnel_modem_dl_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@...05000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x11005000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ funnel_modem_dl_in0: endpoint {
+ remote-endpoint = <&tpda_modem_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_modem_dl_out: endpoint {
+ remote-endpoint = <&tn_ag_in13>;
+ };
+ };
+ };
+ };
+
+ tpdm@...2c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1102c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_gcc_out: endpoint {
+ remote-endpoint = <&tn_ag_in17>;
+ };
+ };
+ };
+ };
+
+ tpdm@...80000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11180000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_out: endpoint {
+ remote-endpoint = <&tpda_cdsp_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@...83000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11183000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_cmsr1_out: endpoint {
+ remote-endpoint = <&tpda_cdsp_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@...84000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11184000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_cmsr2_out: endpoint {
+ remote-endpoint = <&tpda_cdsp_in4>;
+ };
+ };
+ };
+ };
+
+ tpdm@...85000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11185000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_dpm1_out: endpoint {
+ remote-endpoint = <&tpda_cdsp_in5>;
+ };
+ };
+ };
+ };
+
+ tpdm@...86000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11186000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_dpm2_out: endpoint {
+ remote-endpoint = <&tpda_cdsp_in6>;
+ };
+ };
+ };
+ };
+
+ tpda@...88000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x11188000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_cdsp_in0: endpoint {
+ remote-endpoint = <&tpdm_cdsp_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_cdsp_in1: endpoint {
+ remote-endpoint = <&tpdm_cdsp_llm_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_cdsp_in2: endpoint {
+ remote-endpoint = <&tpdm_cdsp_llm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ tpda_cdsp_in3: endpoint {
+ remote-endpoint = <&tpdm_cdsp_cmsr1_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ tpda_cdsp_in4: endpoint {
+ remote-endpoint = <&tpdm_cdsp_cmsr2_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ tpda_cdsp_in5: endpoint {
+ remote-endpoint = <&tpdm_cdsp_dpm1_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ tpda_cdsp_in6: endpoint {
+ remote-endpoint = <&tpdm_cdsp_dpm2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_cdsp_out: endpoint {
+ remote-endpoint = <&funnel_cdsp_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@...89000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x11189000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ funnel_cdsp_in0: endpoint {
+ remote-endpoint = <&tpda_cdsp_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_cdsp_out: endpoint {
+ remote-endpoint = <&tn_ag_in16>;
+ };
+ };
+ };
+ };
+
+ tpdm@...a3000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111a3000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_pmu_out: endpoint {
+ remote-endpoint = <&tn_ag_in29>;
+ };
+ };
+ };
+ };
+
+ tpdm@...a4000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111a4000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_qrng_out: endpoint {
+ remote-endpoint = <&tn_ag_in18>;
+ };
+ };
+ };
+ };
+
+ tpdm@...a5000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111a5000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_dlmm_out: endpoint {
+ remote-endpoint = <&tn_ag_in25>;
+ };
+ };
+ };
+ };
+
+ tpdm@...a6000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111a6000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_north_dsb_out: endpoint {
+ remote-endpoint = <&tn_ag_in26>;
+ };
+ };
+ };
+ };
+
+ tpdm@...a7000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111a7000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_south_dsb_out: endpoint {
+ remote-endpoint = <&tn_ag_in27>;
+ };
+ };
+ };
+ };
+
+ tpdm@...a8000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111a8000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_rdpm_cmb0_out: endpoint {
+ remote-endpoint = <&tn_ag_in30>;
+ };
+ };
+ };
+ };
+
+ tpdm@...a9000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111a9000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_rdpm_cmb1_out: endpoint {
+ remote-endpoint = <&tn_ag_in31>;
+ };
+ };
+ };
+ };
+
+ tpdm@...aa000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111aa000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_rdpm_cmb2_out: endpoint {
+ remote-endpoint = <&tn_ag_in32>;
+ };
+ };
+ };
+ };
+
+ tpdm@...ab000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111ab000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_ipcc_cmb0_out: endpoint {
+ remote-endpoint = <&tn_ag_in36>;
+ };
+ };
+ };
+ };
+
+ tpdm@...ac000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111ac000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_ipcc_cmb1_out: endpoint {
+ remote-endpoint = <&tn_ag_in28>;
+ };
+ };
+ };
+ };
+
+ tpdm@...ad000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111ad000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_ipcc_cmb2_out: endpoint {
+ remote-endpoint = <&tn_ag_in34>;
+ };
+ };
+ };
+ };
+
+ tpdm@...ae000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111ae000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_ipcc_cmb3_out: endpoint {
+ remote-endpoint = <&tn_ag_in37>;
+ };
+ };
+ };
+ };
+
+ tpdm@...af000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111af000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_ipcc_cmb4_out: endpoint {
+ remote-endpoint = <&tn_ag_in35>;
+ };
+ };
+ };
+ };
+
+ tpdm@...b3000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111b3000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_pcie_rscc_out: endpoint {
+ remote-endpoint = <&tn_ag_in8>;
+ };
+ };
+ };
+ };
+
+ tn@...b8000 {
+ compatible = "qcom,coresight-tnoc", "arm,primecell";
+ reg = <0x0 0x111b8000 0x0 0x4200>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@8 {
+ reg = <8>;
+
+ tn_ag_in8: endpoint {
+ remote-endpoint = <&tpdm_pcie_rscc_out>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ tn_ag_in13: endpoint {
+ remote-endpoint = <&funnel_modem_dl_out>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ tn_ag_in16: endpoint {
+ remote-endpoint = <&funnel_cdsp_out>;
+ };
+ };
+
+ port@11 {
+ reg = <0x11>;
+
+ tn_ag_in17: endpoint {
+ remote-endpoint = <&tpdm_gcc_out>;
+ };
+ };
+
+ port@12 {
+ reg = <0x12>;
+
+ tn_ag_in18: endpoint {
+ remote-endpoint = <&tpdm_qrng_out>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ tn_ag_in19: endpoint {
+ remote-endpoint = <&tpdm_qm_out>;
+ };
+ };
+
+ port@15 {
+ reg = <0x15>;
+
+ tn_ag_in21: endpoint {
+ remote-endpoint = <&tpdm_ipa_out>;
+ };
+ };
+
+ port@19 {
+ reg = <0x19>;
+
+ tn_ag_in25: endpoint {
+ remote-endpoint = <&tpdm_dlmm_out>;
+ };
+ };
+
+ port@1a {
+ reg = <0x1a>;
+
+ tn_ag_in26: endpoint {
+ remote-endpoint = <&tpdm_north_dsb_out>;
+ };
+ };
+
+ port@1b {
+ reg = <0x1b>;
+
+ tn_ag_in27: endpoint {
+ remote-endpoint = <&tpdm_south_dsb_out>;
+ };
+ };
+
+ port@1c {
+ reg = <0x1c>;
+
+ tn_ag_in28: endpoint {
+ remote-endpoint = <&tpdm_ipcc_cmb1_out>;
+ };
+ };
+
+ port@1d {
+ reg = <0x1d>;
+
+ tn_ag_in29: endpoint {
+ remote-endpoint = <&tpdm_pmu_out>;
+ };
+ };
+
+ port@1e {
+ reg = <0x1e>;
+
+ tn_ag_in30: endpoint {
+ remote-endpoint = <&tpdm_rdpm_cmb0_out>;
+ };
+ };
+
+ port@1f {
+ reg = <0x1f>;
+
+ tn_ag_in31: endpoint {
+ remote-endpoint = <&tpdm_rdpm_cmb1_out>;
+ };
+ };
+
+ port@20 {
+ reg = <0x20>;
+
+ tn_ag_in32: endpoint {
+ remote-endpoint = <&tpdm_rdpm_cmb2_out>;
+ };
+ };
+
+ port@22 {
+ reg = <0x22>;
+
+ tn_ag_in34: endpoint {
+ remote-endpoint = <&tpdm_ipcc_cmb2_out>;
+ };
+ };
+
+ port@23 {
+ reg = <0x23>;
+
+ tn_ag_in35: endpoint {
+ remote-endpoint = <&tpdm_ipcc_cmb4_out>;
+ };
+ };
+
+ port@24 {
+ reg = <0x24>;
+
+ tn_ag_in36: endpoint {
+ remote-endpoint = <&tpdm_ipcc_cmb0_out>;
+ };
+ };
+
+ port@25 {
+ reg = <37>;
+
+ tn_ag_in37: endpoint {
+ remote-endpoint = <&tpdm_ipcc_cmb3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tn_ag_out: endpoint {
+ remote-endpoint = <&funnel_in0_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@...d0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_qm_out: endpoint {
+ remote-endpoint = <&tn_ag_in19>;
+ };
+ };
+ };
+ };
+
+ tpdm@...03000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11303000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio4_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in4>;
+ };
+ };
+ };
+ };
+
+ funnel@...04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x11304000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@5 {
+ reg = <5>;
+
+ funnel_aoss_in5: endpoint {
+ remote-endpoint = <&tpda_aoss_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ funnel_aoss_in6: endpoint {
+ remote-endpoint = <&funnel_in0_out>;
+ };
+ };
+
+ };
+
+ out-ports {
+ port {
+ funnel_aoss_out: endpoint {
+ remote-endpoint = <&tmc_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@...05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x11305000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ tmc_etf_in: endpoint {
+ remote-endpoint = <&funnel_aoss_out>;
+ };
+ };
+ };
+ };
+
+ tpda@...08000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x11308000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_aoss_in0: endpoint {
+ remote-endpoint = <&tpdm_swao_prio0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_aoss_in1: endpoint {
+ remote-endpoint = <&tpdm_swao_prio1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_aoss_in2: endpoint {
+ remote-endpoint = <&tpdm_swao_prio2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ tpda_aoss_in3: endpoint {
+ remote-endpoint = <&tpdm_swao_prio3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ tpda_aoss_in4: endpoint {
+ remote-endpoint = <&tpdm_swao_prio4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ tpda_aoss_in5: endpoint {
+ remote-endpoint = <&tpdm_swao_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_aoss_out: endpoint {
+ remote-endpoint = <&funnel_aoss_in5>;
+ };
+ };
+ };
+ };
+
+ tpdm@...09000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11309000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio0_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@...0a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1130a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio1_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@...0b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1130b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio2_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm@...0c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1130c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio3_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@...0d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1130d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in5>;
+ };
+ };
+ };
+ };
+
+ tpdm@...22000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11422000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_ipa_out: endpoint {
+ remote-endpoint = <&tn_ag_in21>;
+ };
+ };
+ };
+ };
+
sram@...80000 {
compatible = "qcom,kaanapali-imem", "mmio-sram";
reg = <0x0 0x14680000 0x0 0x1000>;
@@ -1603,4 +2711,56 @@ timer {
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
+
+ tpdm-cdsp-llm {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_llm_out: endpoint {
+ remote-endpoint = <&tpda_cdsp_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm-cdsp-llm2 {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_cdsp_llm2_out: endpoint {
+ remote-endpoint = <&tpda_cdsp_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm-modem1 {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_modem1_out: endpoint {
+ remote-endpoint = <&tpda_modem_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm-modem2 {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <64>;
+
+ out-ports {
+ port {
+ tpdm_modem2_out: endpoint {
+ remote-endpoint = <&tpda_modem_in2>;
+ };
+ };
+ };
+ };
};
--
2.25.1
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