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Message-ID: <aU4aSrhA+Ygdibjj@intel.com>
Date: Fri, 26 Dec 2025 13:16:58 +0800
From: Chao Gao <chao.gao@...el.com>
To: Sean Christopherson <seanjc@...gle.com>
CC: Paolo Bonzini <pbonzini@...hat.com>, <kvm@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, Dongli Zhang <dongli.zhang@...cle.com>
Subject: Re: [PATCH v3 10/10] KVM: x86: Update APICv ISR (a.k.a. SVI) as part
 of kvm_apic_update_apicv()

On Fri, Dec 05, 2025 at 03:19:13PM -0800, Sean Christopherson wrote:
>Fold the calls to .hwapic_isr_update() in kvm_apic_set_state() and
>__kvm_vcpu_update_apicv() into kvm_apic_update_apicv(), as updating SVI is
>directly related to updating KVM's own cache of ISR information, e.g.
>SVI is more or less the APICv equivalent of highest_isr_cache.
>
>Note, calling .hwapic_isr_update() during kvm_apic_update_apicv() has two
>benign side effects.  First, it adds a call during kvm_lapic_reset(), but
>that's a glorified nop as the ISR has already been zeroed.  Second, it
>changes the order between .hwapic_isr_update() and
>.apicv_post_state_restore() in kvm_apic_set_state(), but the former is
>VMX-only and the latter is SVM-only, i.e. is also a glorified nop.
>
>Signed-off-by: Sean Christopherson <seanjc@...gle.com>

Reviewed-by: Chao Gao <chao.gao@...el.com>

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