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Message-ID: <CAGsJ_4xssfB7hNOWLDianQfx+9wC2e4qZKtRBUzEZ-v97Sa63Q@mail.gmail.com>
Date: Sun, 28 Dec 2025 09:59:18 +1300
From: Barry Song <21cnbao@...il.com>
To: Leon Romanovsky <leon@...nel.org>
Cc: catalin.marinas@....com, m.szyprowski@...sung.com, robin.murphy@....com,
will@...nel.org, iommu@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, xen-devel@...ts.xenproject.org,
Ada Couprie Diaz <ada.coupriediaz@....com>, Ard Biesheuvel <ardb@...nel.org>, Marc Zyngier <maz@...nel.org>,
Anshuman Khandual <anshuman.khandual@....com>, Ryan Roberts <ryan.roberts@....com>,
Suren Baghdasaryan <surenb@...gle.com>, Joerg Roedel <joro@...tes.org>,
Tangquan Zheng <zhengtangquan@...o.com>
Subject: Re: [PATCH RFC v2 8/8] dma-iommu: Support DMA sync batch mode for
iommu_dma_sync_sg_for_{cpu, device}
On Sun, Dec 28, 2025 at 9:16 AM Leon Romanovsky <leon@...nel.org> wrote:
>
> On Sat, Dec 27, 2025 at 11:52:48AM +1300, Barry Song wrote:
> > From: Barry Song <baohua@...nel.org>
> >
> > Apply batched DMA synchronization to iommu_dma_sync_sg_for_cpu() and
> > iommu_dma_sync_sg_for_device(). For all buffers in an SG list, only
> > a single flush operation is needed.
> >
> > I do not have the hardware to test this, so the patch is marked as
> > RFC. I would greatly appreciate any testing feedback.
> >
> > Cc: Leon Romanovsky <leon@...nel.org>
> > Cc: Marek Szyprowski <m.szyprowski@...sung.com>
> > Cc: Catalin Marinas <catalin.marinas@....com>
> > Cc: Will Deacon <will@...nel.org>
> > Cc: Ada Couprie Diaz <ada.coupriediaz@....com>
> > Cc: Ard Biesheuvel <ardb@...nel.org>
> > Cc: Marc Zyngier <maz@...nel.org>
> > Cc: Anshuman Khandual <anshuman.khandual@....com>
> > Cc: Ryan Roberts <ryan.roberts@....com>
> > Cc: Suren Baghdasaryan <surenb@...gle.com>
> > Cc: Robin Murphy <robin.murphy@....com>
> > Cc: Joerg Roedel <joro@...tes.org>
> > Cc: Tangquan Zheng <zhengtangquan@...o.com>
> > Signed-off-by: Barry Song <baohua@...nel.org>
> > ---
> > drivers/iommu/dma-iommu.c | 15 +++++++--------
> > 1 file changed, 7 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
> > index ffa940bdbbaf..b68dbfcb7846 100644
> > --- a/drivers/iommu/dma-iommu.c
> > +++ b/drivers/iommu/dma-iommu.c
> > @@ -1131,10 +1131,9 @@ void iommu_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
> > iommu_dma_sync_single_for_cpu(dev, sg_dma_address(sg),
> > sg->length, dir);
> > } else if (!dev_is_dma_coherent(dev)) {
> > - for_each_sg(sgl, sg, nelems, i) {
> > + for_each_sg(sgl, sg, nelems, i)
> > arch_sync_dma_for_cpu(sg_phys(sg), sg->length, dir);
> > - arch_sync_dma_flush();
> > - }
> > + arch_sync_dma_flush();
>
> This and previous patches should be squashed into the one which
> introduced arch_sync_dma_flush().
Hi Leon,
The series is structured to first introduce no functional change by
replacing all arch_sync_dma_for_* calls with arch_sync_dma_for_* plus
arch_sync_dma_flush(). Subsequent patches then add batching for
different scenarios as separate changes.
Another issue is that I was unable to find a board that both runs
mainline and exercises the IOMMU paths affected by these changes.
As a result, patches 7 and 8 are marked as RFC, while the other
patches have been tested on a real board running mainline + changes.
Thanks
Barry
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