linux-kernel - Re: [PATCH] PCI: qcom: Clear ASPM L0s CAP for MSM8996 SoC

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Message-ID: <scgyvnbmovko24h3sesnmt3mlnujvxohgpeusadusn3fkhsqv3@4hsnd7oacepy>
Date: Sat, 27 Dec 2025 09:58:28 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>, 
	lpieralisi@...nel.org, kwilczynski@...nel.org, bhelgaas@...gle.com, robh@...nel.org, 
	linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>, Val Packett <val@...kett.cool>
Subject: Re: [PATCH] PCI: qcom: Clear ASPM L0s CAP for MSM8996 SoC

On Fri, Dec 26, 2025 at 05:39:55PM -0600, Bjorn Helgaas wrote:
> [+cc Val]
> 
> On Wed, Nov 26, 2025 at 01:47:18PM +0530, Manivannan Sadhasivam wrote:
> > From: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
> > 
> > Though I couldn't confirm the ASPM L0s support with the Qcom hardware team,
> > bug report from Dmitry suggests that L0s is broken on this legacy SoC.
> > Hence, clear the L0s CAP for the Root Ports in this SoC.
> 
> I'm squinting a little bit about a Qcom engineer not being able to
> confirm whether L0s is known to work on a Qcom part :)
> 

Unfortunately, all the folks who worked on this part no longer work at Qcom. And
there is no credible documentation that affirms me that L0s is supported on this
SoC.

> This looks like possible v6.19 material since it's a regression and
> Dmitry reported random resets that are impossible to debug?
> 

Yes. I was about to ping you offline the list of v6.19 materials once you got
back from vacation.

- Mani

> For now I moved this to the beginning of pci/controller/dwc-qcom since
> it sounds like the PERST# series will be updated.
> 
> > Since qcom_pcie_clear_aspm_l0s() is now used by more than one SoC config,
> > call it from qcom_pcie_host_init() instead.
> > 
> > Reported-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
> > Closes: https://lore.kernel.org/linux-pci/4cp5pzmlkkht2ni7us6p3edidnk25l45xrp6w3fxguqcvhq2id@wjqqrdpkypkf
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 805edbbfe7eb..25399d47fc40 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -1088,7 +1088,6 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
> >  		writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
> >  				pcie->parf + PARF_NO_SNOOP_OVERRIDE);
> >  
> > -	qcom_pcie_clear_aspm_l0s(pcie->pci);
> >  	qcom_pcie_clear_hpc(pcie->pci);
> >  
> >  	return 0;
> > @@ -1350,6 +1349,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
> >  			goto err_disable_phy;
> >  	}
> >  
> > +	qcom_pcie_clear_aspm_l0s(pcie->pci);
> > +
> >  	qcom_ep_reset_deassert(pcie);
> >  
> >  	if (pcie->cfg->ops->config_sid) {
> > @@ -1486,6 +1487,7 @@ static const struct qcom_pcie_cfg cfg_2_1_0 = {
> >  
> >  static const struct qcom_pcie_cfg cfg_2_3_2 = {
> >  	.ops = &ops_2_3_2,
> > +	.no_l0s = true,
> >  };
> >  
> >  static const struct qcom_pcie_cfg cfg_2_3_3 = {
> > -- 
> > 2.48.1
> > 

-- 
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