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Message-ID: <20251229075313.27254-4-eleanor.lin@realtek.com>
Date: Mon, 29 Dec 2025 15:53:07 +0800
From: Yu-Chun Lin <eleanor.lin@...ltek.com>
To: <mturquette@...libre.com>, <sboyd@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <p.zabel@...gutronix.de>,
<cylee12@...ltek.com>, <jyanchou@...ltek.com>
CC: <devicetree@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <james.tai@...ltek.com>,
<cy.huang@...ltek.com>, <stanley_chang@...ltek.com>,
<eleanor.lin@...ltek.com>
Subject: [PATCH 3/9] clk: realtek: Introduce a common probe()
Add rtk_clk_probe() to set up the shared regmap, register clock hardware,
add the clock provider, and optionally register a reset controller when
reset bank data is provided.
Signed-off-by: Cheng-Yu Lee <cylee12@...ltek.com>
Signed-off-by: Yu-Chun Lin <eleanor.lin@...ltek.com>
---
drivers/clk/realtek/Makefile | 1 +
drivers/clk/realtek/common.c | 72 ++++++++++++++++++++++++++++++++++++
drivers/clk/realtek/common.h | 40 ++++++++++++++++++++
3 files changed, 113 insertions(+)
create mode 100644 drivers/clk/realtek/common.c
create mode 100644 drivers/clk/realtek/common.h
diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
index 52267de2eef4..4041951b7c62 100644
--- a/drivers/clk/realtek/Makefile
+++ b/drivers/clk/realtek/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o
+clk-rtk-y += common.o
clk-rtk-y += reset.o
diff --git a/drivers/clk/realtek/common.c b/drivers/clk/realtek/common.c
new file mode 100644
index 000000000000..df89d2a10291
--- /dev/null
+++ b/drivers/clk/realtek/common.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2019 Realtek Semiconductor Corporation
+ * Author: Cheng-Yu Lee <cylee12@...ltek.com>
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include "common.h"
+
+int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc)
+{
+ int i, ret;
+ struct device *dev = &pdev->dev;
+ struct rtk_reset_initdata reset_initdata = { 0 };
+
+ struct regmap *regmap = device_node_to_regmap(pdev->dev.of_node);
+
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ dev_err(dev, "Failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ for (i = 0; i < desc->num_clks; i++)
+ desc->clks[i]->regmap = regmap;
+
+ for (i = 0; i < desc->clk_data->num; i++) {
+ struct clk_hw *hw = desc->clk_data->hws[i];
+
+ if (!hw)
+ continue;
+
+ ret = devm_clk_hw_register(dev, hw);
+
+ if (ret) {
+ dev_warn(dev, "failed to register hw of clk%d: %d\n", i,
+ ret);
+ desc->clk_data->hws[i] = NULL;
+ }
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ desc->clk_data);
+
+ if (ret) {
+ dev_err(dev, "Failed to add clock provider\n");
+ return ret;
+ }
+
+ if (!desc->num_reset_banks)
+ return 0;
+
+ if (!desc->reset_banks) {
+ dev_err(dev,
+ "Missing reset banks data though num_reset_banks is %lu\n",
+ desc->num_reset_banks);
+ return -EINVAL;
+ }
+
+ reset_initdata.regmap = regmap;
+ reset_initdata.num_banks = desc->num_reset_banks;
+ reset_initdata.banks = desc->reset_banks;
+
+ return rtk_reset_controller_add(dev, &reset_initdata);
+}
+EXPORT_SYMBOL_GPL(rtk_clk_probe);
+
+MODULE_DESCRIPTION("Realtek clock infrastructure");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/realtek/common.h b/drivers/clk/realtek/common.h
new file mode 100644
index 000000000000..7b700f144e9e
--- /dev/null
+++ b/drivers/clk/realtek/common.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2016-2019 Realtek Semiconductor Corporation
+ * Author: Cheng-Yu Lee <cylee12@...ltek.com>
+ */
+
+#ifndef __CLK_REALTEK_COMMON_H
+#define __CLK_REALTEK_COMMON_H
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/hwspinlock.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+#include "reset.h"
+
+struct device;
+struct platform_device;
+
+struct clk_regmap {
+ struct clk_hw hw;
+ struct regmap *regmap;
+};
+
+#define to_clk_regmap(_hw) container_of(_hw, struct clk_regmap, hw)
+#define __clk_regmap_hw(_p) ((_p)->hw)
+
+struct rtk_clk_desc {
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_regmap **clks;
+ size_t num_clks;
+ struct rtk_reset_bank *reset_banks;
+ size_t num_reset_banks;
+};
+
+int rtk_clk_probe(struct platform_device *pdev,
+ const struct rtk_clk_desc *desc);
+
+#endif /* __CLK_REALTEK_COMMON_H */
--
2.34.1
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