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Message-Id: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com>
Date: Tue, 30 Dec 2025 11:03:00 -0300
From: Nícolas F. R. A. Prado <nfraprado@...labora.com>
To: Chun-Kuang Hu <chunkuang.hu@...nel.org>, 
 Philipp Zabel <p.zabel@...gutronix.de>, David Airlie <airlied@...il.com>, 
 Simona Vetter <simona@...ll.ch>, Matthias Brugger <matthias.bgg@...il.com>, 
 AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>, 
 Justin Green <greenjustin@...omium.org>
Cc: kernel@...labora.com, dri-devel@...ts.freedesktop.org, 
 linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org, 
 linux-arm-kernel@...ts.infradead.org, ariel.dalessandro@...labora.com, 
 daniels@...labora.com, kernel@...labora.com, Nancy.Lin@...iatek.com, 
 Jason-JH.Lin@...iatek.com, 
 Nícolas F. R. A. Prado <nfraprado@...labora.com>
Subject: [PATCH RFC 0/6] AFBC fixes for MediaTek DRM

This series contains a handful of fixes for AFBC support on the MediaTek
DRM driver so that it can be re-enabled.

This is sent as an RFC because there are still some issues to work out
before the series can be merged:

1. Patch 4, 'drm/mediatek: ovl: Disallow AFBC buffers with width over
   1920' did not behave well when tested with Weston, so a better
   solution probably needs to be implemented before this can be merged.

2. Remaining AFBC issues:
   
   a. The first 4 pixel rows are always skipped in the displayed output,
      that is, the first displayed pixel, on the top-left corner,
      corresponds to 4x0. And below the end of the displayed output, the
      first 4x32 pixels are displayed.

   b. On some resolutions, there are still artifacts that look like
      misalignment issues, eg 1024x1080, 1080x1080.

   c. On some resolutions, no output at all is displayed, eg 1920x1080.

Tested on the MT8195-Tomato Chromebook.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@...labora.com>
---
Ariel D'Alessandro (1):
      drm/mediatek: ovl: Fix misaligned layer source size on AFBC mode

Nícolas F. R. A. Prado (5):
      drm/mediatek: plane: Remove extra block from AFBC data payload offset
      drm/mediatek: plane: Correct AFBC alignment definition to 128
      drm/mediatek: ovl: Disallow AFBC buffers with width over 1920
      drm/mediatek: ovl: Disable AFBC on MT8188
      drm/mediatek: Re-enable AFBC support on MediaTek DRM driver

 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 59 ++++++++++++++++++++++++++++++---
 drivers/gpu/drm/mediatek/mtk_plane.c    | 48 +++++++++++++++++++++++++--
 drivers/gpu/drm/mediatek/mtk_plane.h    |  6 +++-
 3 files changed, 104 insertions(+), 9 deletions(-)
---
base-commit: 6f47c4646bee47319cc0980c693ed695c4cfd395
change-id: 20251229-mtk-afbc-fixes-b656f92bc2af

Best regards,
-- 
Nícolas F. R. A. Prado <nfraprado@...labora.com>


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