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Message-ID: <20251231224233.113839-6-zide.chen@intel.com>
Date: Wed, 31 Dec 2025 14:42:22 -0800
From: Zide Chen <zide.chen@...el.com>
To: Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Andi Kleen <ak@...ux.intel.com>,
Eranian Stephane <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org,
Dapeng Mi <dapeng1.mi@...ux.intel.com>,
Zide Chen <zide.chen@...el.com>,
Xudong Hao <xudong.hao@...el.com>,
Falcon Thomas <thomas.falcon@...el.com>
Subject: [PATCH V2 05/13] perf/x86/intel/uncore: Add CBB PMON support for Diamond Rapids
On DMR, PMON units inside the Core Building Block (CBB) are enumerated
separately from those in the Integrated Memory and I/O Hub (IMH).
A new per-CBB MSR (0x710) is introduced for discovery table enumeration.
For counter control registers, the tid_en bit (bit 16) exists on CBO,
SBO, and Santa, but it is not used by any events. Mark this bit as
reserved.
Similarly, disallow extended umask (bits 32–63) on Santa and sNCU.
Additionally, ignore broken SB2UCIE unit.
Reviewed-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>
Signed-off-by: Zide Chen <zide.chen@...el.com>
---
V2:
- Rename DMR_UNCORE_DISCOVERY_MSR to CBB_UNCORE_DISCOVERY_MSR to
reflect that the MSR is not DMR-specific and allow reuse on future
platforms.
arch/x86/events/intel/uncore.c | 2 +
arch/x86/events/intel/uncore.h | 1 +
arch/x86/events/intel/uncore_discovery.h | 2 +
arch/x86/events/intel/uncore_snbep.c | 52 ++++++++++++++++++++++--
4 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index dc2b2b272bc8..1565c0418fb1 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -1837,6 +1837,8 @@ static const struct uncore_plat_init dmr_uncore_init __initconst = {
.domain[0].base_is_pci = true,
.domain[0].discovery_base = DMR_UNCORE_DISCOVERY_TABLE_DEVICE,
.domain[0].units_ignore = dmr_uncore_imh_units_ignore,
+ .domain[1].discovery_base = CBB_UNCORE_DISCOVERY_MSR,
+ .domain[1].units_ignore = dmr_uncore_cbb_units_ignore,
};
static const struct uncore_plat_init generic_uncore_init __initconst = {
diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
index 1e4b3a22403c..83d01a9cefc0 100644
--- a/arch/x86/events/intel/uncore.h
+++ b/arch/x86/events/intel/uncore.h
@@ -615,6 +615,7 @@ extern struct event_constraint uncore_constraint_empty;
extern int spr_uncore_units_ignore[];
extern int gnr_uncore_units_ignore[];
extern int dmr_uncore_imh_units_ignore[];
+extern int dmr_uncore_cbb_units_ignore[];
/* uncore_snb.c */
int snb_uncore_pci_init(void);
diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/intel/uncore_discovery.h
index 618788c30ac6..63b8f7634e42 100644
--- a/arch/x86/events/intel/uncore_discovery.h
+++ b/arch/x86/events/intel/uncore_discovery.h
@@ -2,6 +2,8 @@
/* Store the full address of the global discovery table */
#define UNCORE_DISCOVERY_MSR 0x201e
+/* Base address of uncore perfmon discovery table for CBB domain */
+#define CBB_UNCORE_DISCOVERY_MSR 0x710
/* Generic device ID of a discovery table device */
#define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 4b72560dc13f..df173534637a 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -6807,6 +6807,28 @@ static struct intel_uncore_type dmr_uncore_hamvf = {
.attr_update = uncore_alias_groups,
};
+static struct intel_uncore_type dmr_uncore_cbo = {
+ .name = "cbo",
+ .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
+ .format_group = &dmr_sca_uncore_format_group,
+ .attr_update = uncore_alias_groups,
+};
+
+static struct intel_uncore_type dmr_uncore_santa = {
+ .name = "santa",
+ .attr_update = uncore_alias_groups,
+};
+
+static struct intel_uncore_type dmr_uncore_cncu = {
+ .name = "cncu",
+ .attr_update = uncore_alias_groups,
+};
+
+static struct intel_uncore_type dmr_uncore_sncu = {
+ .name = "sncu",
+ .attr_update = uncore_alias_groups,
+};
+
static struct intel_uncore_type dmr_uncore_ula = {
.name = "ula",
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
@@ -6814,6 +6836,20 @@ static struct intel_uncore_type dmr_uncore_ula = {
.attr_update = uncore_alias_groups,
};
+static struct intel_uncore_type dmr_uncore_dda = {
+ .name = "dda",
+ .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
+ .format_group = &dmr_sca_uncore_format_group,
+ .attr_update = uncore_alias_groups,
+};
+
+static struct intel_uncore_type dmr_uncore_sbo = {
+ .name = "sbo",
+ .event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
+ .format_group = &dmr_sca_uncore_format_group,
+ .attr_update = uncore_alias_groups,
+};
+
static struct intel_uncore_type dmr_uncore_ubr = {
.name = "ubr",
.event_mask_ext = DMR_HAMVF_EVENT_MASK_EXT,
@@ -6902,10 +6938,15 @@ static struct intel_uncore_type *dmr_uncores[UNCORE_DMR_NUM_UNCORE_TYPES] = {
NULL, NULL, NULL,
NULL, NULL,
&dmr_uncore_hamvf,
- NULL,
- NULL, NULL, NULL,
+ &dmr_uncore_cbo,
+ &dmr_uncore_santa,
+ &dmr_uncore_cncu,
+ &dmr_uncore_sncu,
&dmr_uncore_ula,
- NULL, NULL, NULL, NULL,
+ &dmr_uncore_dda,
+ NULL,
+ &dmr_uncore_sbo,
+ NULL,
NULL, NULL, NULL,
&dmr_uncore_ubr,
NULL,
@@ -6923,6 +6964,11 @@ int dmr_uncore_imh_units_ignore[] = {
UNCORE_IGNORE_END
};
+int dmr_uncore_cbb_units_ignore[] = {
+ 0x25, /* SB2UCIE */
+ UNCORE_IGNORE_END
+};
+
int dmr_uncore_pci_init(void)
{
uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL,
--
2.52.0
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