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Message-ID: <20260102131819.123745-1-linux.amoon@gmail.com>
Date: Fri,  2 Jan 2026 18:47:50 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof WilczyƄski <kwilczynski@...nel.org>,
	Manivannan Sadhasivam <mani@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Heiko Stuebner <heiko@...ech.de>,
	Niklas Cassel <cassel@...nel.org>,
	Shawn Lin <shawn.lin@...k-chips.com>,
	Hans Zhang <18255117159@....com>,
	Nicolas Frattaroli <nicolas.frattaroli@...labora.com>,
	linux-pci@...r.kernel.org (open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS),
	linux-arm-kernel@...ts.infradead.org (moderated list:ARM/Rockchip SoC support),
	linux-rockchip@...ts.infradead.org (open list:ARM/Rockchip SoC support),
	linux-kernel@...r.kernel.org (open list)
Cc: Anand Moon <linux.amoon@...il.com>
Subject: [PATCH v2] PCI: dw-rockchip: Add runtime PM support to Rockchip PCIe

Add runtime powwe manageement functionality into the Rockchip DesignWare
PCIe controller driver. Calling devm_pm_runtime_enable() during device
probing allows the controller to report its runtime PM status, enabling
power management controls to be applied consistently across the entire
connected PCIe hierarchy.

Signed-off-by: Anand Moon <linux.amoon@...il.com>
---
v2:
   improve the commit message
   Drop the .remove patch
   Drop the disable_pm_runtime
v1:
 https://lore.kernel.org/all/20251027145602.199154-3-linux.amoon@gmail.com/
---
 drivers/pci/controller/dwc/pcie-dw-rockchip.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index f8605fe61a415..2498ff5146a5a 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -20,6 +20,7 @@
 #include <linux/of_irq.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/reset.h>
 
@@ -709,6 +710,20 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 	if (ret)
 		goto deinit_phy;
 
+	ret = pm_runtime_set_suspended(dev);
+	if (ret)
+		goto deinit_clk;
+
+	ret = devm_pm_runtime_enable(dev);
+	if (ret) {
+		ret = dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
+		goto deinit_clk;
+	}
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret)
+		goto deinit_clk;
+
 	switch (data->mode) {
 	case DW_PCIE_RC_TYPE:
 		ret = rockchip_pcie_configure_rc(pdev, rockchip);
@@ -730,6 +745,8 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
 
 deinit_clk:
 	clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
+	pm_runtime_disable(dev);
+	pm_runtime_no_callbacks(dev);
 deinit_phy:
 	rockchip_pcie_phy_deinit(rockchip);
 

base-commit: b69053dd3ffbc0d2dedbbc86182cdef6f641fe1b
-- 
2.50.1


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