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Message-ID: <20260102155341.3682013-3-olek2@wp.pl>
Date: Fri, 2 Jan 2026 16:47:35 +0100
From: Aleksander Jan Bajkowski <olek2@...pl>
To: benjamin.larsson@...exis.eu,
chester.a.unal@...nc9.com,
davem@...emloft.net,
angelogioacchino.delregno@...labora.com,
ansuelsmth@...il.com,
conor+dt@...nel.org,
herbert@...dor.apana.org.au,
krzk+dt@...nel.org,
matthias.bgg@...il.com,
robh@...nel.org,
sergio.paracuellos@...il.com,
tsbogend@...ha.franken.de,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-crypto@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-mediatek@...ts.infradead.org,
linux-mips@...r.kernel.org
Cc: Aleksander Jan Bajkowski <olek2@...pl>
Subject: [PATCH v3 3/3] mips: dts: ralink: mt7621: add crypto offload support
Add support for the built-in cryptographic accelerator. This accelerator
supports 3DES, AES (128/192/256 bit), ARC4, MD5, SHA1, SHA224, and SHA256.
It also supports full IPSEC, SRTP and TLS offload.
Signed-off-by: Aleksander Jan Bajkowski <olek2@...pl>
---
v3:
- Add reset line and clock gate
- Change commit description
- Wrap long line
---
arch/mips/boot/dts/ralink/mt7621.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index 0704eab4a80b..e1047dd861c0 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -361,6 +361,19 @@ cdmm: cdmm@...f8000 {
reg = <0x1fbf8000 0x8000>;
};
+ crypto@...04000 {
+ compatible = "mediatek,mt7621-eip93",
+ "inside-secure,safexcel-eip93ies";
+ reg = <0x1e004000 0x1000>;
+
+ clocks = <&sysc MT7621_CLK_CRYPTO>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
+
+ resets = <&sysc MT7621_RST_CRYPTO>;
+ };
+
ethernet: ethernet@...00000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
--
2.47.3
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