linux-kernel - Re: [PATCH 1/3] riscv: clocksource: Fix stimecmp update hazard on RV32

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Message-ID: <CAK9=C2XTi9Gjy0oJExGyaVvPbh2+cJzmeea5JnMR4d3kbvDJDA@mail.gmail.com>
Date: Sat, 3 Jan 2026 20:16:01 +0530
From: Anup Patel <apatel@...tanamicro.com>
To: Naohiko Shimizu <naohiko.shimizu@...il.com>
Cc: pjw@...nel.org, palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr, 
	anup@...infault.org, atish.patra@...ux.dev, daniel.lezcano@...aro.org, 
	tglx@...utronix.de, nick.hu@...ive.com, linux-riscv@...ts.infradead.org, 
	linux-kernel@...r.kernel.org, kvm@...r.kernel.org, 
	kvm-riscv@...ts.infradead.org
Subject: Re: [PATCH 1/3] riscv: clocksource: Fix stimecmp update hazard on RV32

On Sat, Jan 3, 2026 at 3:16 PM Naohiko Shimizu
<naohiko.shimizu@...il.com> wrote:

Please add a detailed commit description about why the
new way of programming stimecmp is better. Also, explain
what the current Priv spec says in this context.

>
> Signed-off-by: Naohiko Shimizu <naohiko.shimizu@...il.com>
> ---
>  drivers/clocksource/timer-riscv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 4d7cf338824a..cfc4d83c42c0 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -50,8 +50,9 @@ static int riscv_clock_next_event(unsigned long delta,
>
>         if (static_branch_likely(&riscv_sstc_available)) {
>  #if defined(CONFIG_32BIT)
> -               csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
> +               csr_write(CSR_STIMECMP, ULONG_MAX);
>                 csr_write(CSR_STIMECMPH, next_tval >> 32);
> +               csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
>  #else
>                 csr_write(CSR_STIMECMP, next_tval);
>  #endif
> --
> 2.39.5
>
>

Regards,
Anup