linux-kernel - [PATCH v2 1/3] riscv: clocksource: Fix stimecmp update hazard on RV32

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Message-Id: <20260103152400.552-2-naohiko.shimizu@gmail.com>
Date: Sun,  4 Jan 2026 00:23:58 +0900
From: Naohiko Shimizu <naohiko.shimizu@...il.com>
To: pjw@...nel.org,
	palmer@...belt.com,
	aou@...s.berkeley.edu
Cc: alex@...ti.fr,
	anup@...infault.org,
	atish.patra@...ux.dev,
	daniel.lezcano@...aro.org,
	tglx@...utronix.de,
	nick.hu@...ive.com,
	linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	kvm@...r.kernel.org,
	kvm-riscv@...ts.infradead.org,
	Naohiko Shimizu <naohiko.shimizu@...il.com>
Subject: [PATCH v2 1/3] riscv: clocksource: Fix stimecmp update hazard on RV32

Signed-off-by: Naohiko Shimizu <naohiko.shimizu@...il.com>

riscv: fix timer register update hazard on RV32

On RV32, updating the 64-bit stimecmp (or vstimecmp) CSR requires two
separate 32-bit writes. A race condition exists if the timer triggers
during these two writes.

The RISC-V Privileged Specification (e.g., Section 3.2.1 for mtimecmp)
recommends a specific 3-step sequence to avoid spurious interrupts
when updating 64-bit comparison registers on 32-bit systems:

1. Set the low-order bits (stimecmp) to all ones (ULONG_MAX).
2. Set the high-order bits (stimecmph) to the desired value.
3. Set the low-order bits (stimecmp) to the desired value.

Current implementation writes the LSB first without ensuring a future
value, which may lead to a transient state where the 64-bit comparison
is incorrectly evaluated as "expired" by the hardware. This results in
spurious timer interrupts.

This patch adopts the spec-recommended 3-step sequence to ensure the
intermediate 64-bit state is never smaller than the current time.
---
 drivers/clocksource/timer-riscv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 4d7cf338824a..cfc4d83c42c0 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -50,8 +50,9 @@ static int riscv_clock_next_event(unsigned long delta,
 
 	if (static_branch_likely(&riscv_sstc_available)) {
 #if defined(CONFIG_32BIT)
-		csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
+		csr_write(CSR_STIMECMP, ULONG_MAX);
 		csr_write(CSR_STIMECMPH, next_tval >> 32);
+		csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
 #else
 		csr_write(CSR_STIMECMP, next_tval);
 #endif
-- 
2.39.5