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Message-ID: <180afaec-c9fb-4845-a1b9-6adc7b9c7434@gmail.com>
Date: Sat, 3 Jan 2026 10:20:18 +0530
From: Charan Pedumuru <charan.pedumuru@...il.com>
To: Rob Herring <robh@...nel.org>
Cc: Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>, Vignesh Raghavendra <vigneshr@...com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>, Stefan Agner <stefan@...er.ch>,
Lucas Stach <dev@...xeye.de>, linux-mtd@...ts.infradead.org,
devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3] dt-bindings: mtd: nvidia,tegra20-nand: convert to DT
schema
On 02-01-2026 21:28, Rob Herring wrote:
> On Wed, Dec 31, 2025 at 09:29:32AM +0000, Charan Pedumuru wrote:
>> Convert NVIDIA Tegra NAND Flash Controller binding to YAML format.
>> Changes during Conversion:
>> - Define new properties `power-domains` and `operating-points-v2`
>> because the existing in tree DTS uses them.
>>
>> Signed-off-by: Charan Pedumuru <charan.pedumuru@...il.com>
>> ---
>> Changes in v3:
>> - Removed pattern properties for partition.
>> - Used single quotes for nand string in pattern properties.
>> - Modified maxItems value and added minItems to reg property under nand child node.
>> - Link to v2: https://lore.kernel.org/r/20251229-nvidia-nand-v2-1-b697d9724b0b@gmail.com
>>
>> Changes in v2:
>> - Edited the commit description to match the updated changes.
>> - Modified the description for the YAML.
>> - Removed all the duplicated properties, defined a proper ref for both parent
>> and child nodes.
>> - Removed unnecessary properties from the required following the old
>> text binding.
>> - Link to v1: https://lore.kernel.org/r/20251030-nvidia-nand-v1-1-7614e1428292@gmail.com
>> ---
>> .../bindings/mtd/nvidia,tegra20-nand.yaml | 103 +++++++++++++++++++++
>> .../bindings/mtd/nvidia-tegra20-nand.txt | 64 -------------
>> 2 files changed, 103 insertions(+), 64 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml
>> new file mode 100644
>> index 000000000000..632cfd7dc5e2
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml
>> @@ -0,0 +1,103 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: NVIDIA Tegra NAND Flash Controller
>> +
>> +maintainers:
>> + - Jonathan Hunter <jonathanh@...dia.com>
>> +
>> +allOf:
>> + - $ref: nand-controller.yaml
>> +
>> +description:
>> + The NVIDIA NAND controller provides an interface between NVIDIA SoCs
>> + and raw NAND flash devices. It supports standard NAND operations,
>> + hardware-assisted ECC, OOB data access, and DMA transfers, and
>> + integrates with the Linux MTD NAND subsystem for reliable flash management.
>> +
>> +properties:
>> + compatible:
>> + const: nvidia,tegra20-nand
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + clock-names:
>> + items:
>> + - const: nand
>> +
>> + resets:
>> + maxItems: 1
>> +
>> + reset-names:
>> + items:
>> + - const: nand
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + operating-points-v2:
>> + maxItems: 1
>> +
>> +patternProperties:
>> + '^nand@':
>> + type: object
>> + description: Individual NAND chip connected to the NAND controller
>> + $ref: raw-nand-chip.yaml#
>> +
>> + properties:
>> + reg:
>> + minItems: 1
>> + maxItems: 5
>
> Sigh. I gave you the exact schema to use. How is 5 address ENTRIES
> valid? Again:
>
> reg:
> maximum: 5
Okay, I thought it's an invalid syntax as I never used it to represent reg property before, I will fix it in the next revision. Thanks.
>
> Rob
--
Best Regards,
Charan.
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