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Message-Id: <DFFOSJU7PN4A.KER1R2GT8EYZ@pigmoral.tech>
Date: Sun, 04 Jan 2026 17:11:09 +0800
From: "Junhui Liu" <junhui.liu@...moral.tech>
To: "David Laight" <david.laight.linux@...il.com>, "Junhui Liu"
 <junhui.liu@...moral.tech>
Cc: "Michael Turquette" <mturquette@...libre.com>, "Stephen Boyd"
 <sboyd@...nel.org>, "Rob Herring" <robh@...nel.org>, "Krzysztof Kozlowski"
 <krzk+dt@...nel.org>, "Conor Dooley" <conor+dt@...nel.org>, "Philipp Zabel"
 <p.zabel@...gutronix.de>, "Paul Walmsley" <pjw@...nel.org>, "Palmer
 Dabbelt" <palmer@...belt.com>, "Albert Ou" <aou@...s.berkeley.edu>,
 "Alexandre Ghiti" <alex@...ti.fr>, <linux-clk@...r.kernel.org>,
 <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
 <devicetree@...r.kernel.org>, "Troy Mitchell"
 <troy.mitchell@...ux.spacemit.com>, "Brian Masney" <bmasney@...hat.com>
Subject: Re: [PATCH v4 1/6] clk: correct clk_div_mask() return value for
 width == 32

Hi David,

On Wed Dec 31, 2025 at 6:56 PM CST, David Laight wrote:
> On Wed, 31 Dec 2025 14:40:05 +0800
> Junhui Liu <junhui.liu@...moral.tech> wrote:
>
>> The macro clk_div_mask() currently wraps to zero when width is 32 due to
>> 1 << 32 being undefined behavior. This leads to incorrect mask generation
>> and prevents correct retrieval of register field values for 32-bit-wide
>> dividers.
>> 
>> Although it is unlikely to exhaust all U32_MAX div, some clock IPs may rely
>> on a 32-bit val entry in their div_table to match a div, so providing a
>> full 32-bit mask is necessary.
>> 
>> Fix this by casting 1 to long, ensuring proper behavior for valid widths up
>> to 32.
>> 
>> Reviewed-by: Troy Mitchell <troy.mitchell@...ux.spacemit.com>
>> Reviewed-by: Brian Masney <bmasney@...hat.com>
>> Signed-off-by: Junhui Liu <junhui.liu@...moral.tech>
>> ---
>>  include/linux/clk-provider.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
>> index 630705a47129..a651ccaf1b44 100644
>> --- a/include/linux/clk-provider.h
>> +++ b/include/linux/clk-provider.h
>> @@ -720,7 +720,7 @@ struct clk_divider {
>>  	spinlock_t	*lock;
>>  };
>>  
>> -#define clk_div_mask(width)	((1 << (width)) - 1)
>> +#define clk_div_mask(width)	((1L << (width)) - 1)
>
> That makes no difference on 32bit architectures.

You're right. Thanks for pointing it out.

> I also suspect you need to ensure the value is 'unsigned int'.
> If you can guarantee that width isn't zero (probably true), then:
> #define clk_div_mask(width) ((2u << (width) - 1) - 1)
> should have the desired value for widths 1..32.
> It probably adds an extra instruction.
> (OTOH so does passing width as 'u8'.)
>

Thanks for your suggestion. After further consideration, I prefer using
the standard GENMASK macro instead:

#define clk_div_mask(width) GENMASK((width) - 1, 0)

Using a unified kernel macro is better for maintenance and it also
benefits from the compile time checks in GENMASK for constant inputs.
This approach also supports a width range of 1..32, and even up to 64 on
64-bit architectures.

-- 
Best regards,
Junhui Liu


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