linux-kernel - Re: [PATCH v2] PCI: loongson: Override PCIe bridge supported speeds for older Loongson 3C6000 series steppings

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <9ddf7822-eda7-4c6c-9240-31ab1c4708c3@aosc.io>
Date: Sun, 4 Jan 2026 19:03:14 +0800
From: Mingcong Bai <jeffbai@...c.io>
To: liziyao@...ontech.com, Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Krzysztof Wilczyński <kwilczynski@...nel.org>,
 Manivannan Sadhasivam <mani@...nel.org>, Rob Herring <robh@...nel.org>,
 Bjorn Helgaas <bhelgaas@...gle.com>
Cc: niecheng1@...ontech.com, zhanjun@...ontech.com, guanwentao@...ontech.com,
 Kexy Biscuit <kexybiscuit@...c.io>, linux-pci@...r.kernel.org,
 linux-kernel@...r.kernel.org, Lain Fearyncess Yang <fsf@...e.com>,
 Ayden Meng <aydenmeng@...h.net>, Xi Ruoyao <xry111@...111.site>,
 loongarch@...ts.linux.dev
Subject: Re: [PATCH v2] PCI: loongson: Override PCIe bridge supported speeds
 for older Loongson 3C6000 series steppings

Hi Ziyao Li,

在 2026/1/4 18:00, Ziyao Li via B4 Relay 写道:
> From: Ziyao Li <liziyao@...ontech.com>
> 
> Older steppings of the Loongson 3C6000 series incorrectly report the
> supported link speeds on their PCIe bridges (device IDs 3c19, 3c29) as
> only 2.5 GT/s, despite the upstream bus supporting speeds from 2.5 GT/s
> up to 16 GT/s.
> 
> As a result, certain PCIe devices would be incorrectly probed as a Gen1-
> only, even if higher link speeds are supported, harming performance and
> prevents dynamic link speed functionality from being enabled in drivers
> such as amdgpu.
> 
> Manually override the `supported_speeds` field for affected PCIe bridges
> with those found on the upstream bus to correctly reflect the supported
> link speeds.
> 
> This patch was originally found from AOSC OS[1].

Thanks for the patch. Looping loongarch.

Best Regards,
Mingcong Bai