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Message-ID: <dc5edcc0-0bb9-4ec1-981f-ae9a5530dddd@linux.intel.com>
Date: Sun, 4 Jan 2026 10:26:54 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: Zide Chen <zide.chen@...el.com>, Peter Zijlstra <peterz@...radead.org>,
 Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo <acme@...nel.org>,
 Namhyung Kim <namhyung@...nel.org>, Ian Rogers <irogers@...gle.com>,
 Adrian Hunter <adrian.hunter@...el.com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
 Xudong Hao <xudong.hao@...el.com>, Falcon Thomas <thomas.falcon@...el.com>
Subject: Re: [PATCH V2 06/13] perf/x86/intel/uncore: Add domain global init
 callback


On 1/1/2026 6:42 AM, Zide Chen wrote:
> In the Intel uncore self-describing mechanism, the Global Control
> Register freeze_all bit is SoC-wide and propagates to all uncore PMUs.
>
> On Diamond Rapids, this bit is set at power-on, unlike some prior
> platforms.  Add a global_init callback to unfreeze all PMON units.
>
> Signed-off-by: Zide Chen <zide.chen@...el.com>
> ---
> V2: New patch
>
>  arch/x86/events/intel/uncore.c           | 16 ++++++++++++++++
>  arch/x86/events/intel/uncore.h           |  2 ++
>  arch/x86/events/intel/uncore_discovery.c |  3 +++
>  3 files changed, 21 insertions(+)
>
> diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
> index 1565c0418fb1..080b6870a88d 100644
> --- a/arch/x86/events/intel/uncore.c
> +++ b/arch/x86/events/intel/uncore.c
> @@ -1697,6 +1697,21 @@ static int __init uncore_mmio_init(void)
>  	return ret;
>  }
>  
> +static int uncore_mmio_global_init(u64 ctl)
> +{
> +	void __iomem *io_addr;
> +
> +	io_addr = ioremap(ctl, sizeof(ctl));
> +	if (!io_addr)
> +		return -ENOMEM;
> +
> +	/* Clear bit 0, all other bits are reserved */

Better make the comment clearer, like this.

/* Clear freeze bit (bit 0) to enable all counters. */

Others look good to me.

Reviewed-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>



> +	writel(0, io_addr);
> +
> +	iounmap(io_addr);
> +	return 0;
> +}
> +
>  static const struct uncore_plat_init nhm_uncore_init __initconst = {
>  	.cpu_init = nhm_uncore_cpu_init,
>  };
> @@ -1839,6 +1854,7 @@ static const struct uncore_plat_init dmr_uncore_init __initconst = {
>  	.domain[0].units_ignore = dmr_uncore_imh_units_ignore,
>  	.domain[1].discovery_base = CBB_UNCORE_DISCOVERY_MSR,
>  	.domain[1].units_ignore = dmr_uncore_cbb_units_ignore,
> +	.domain[1].global_init = uncore_mmio_global_init,
>  };
>  
>  static const struct uncore_plat_init generic_uncore_init __initconst = {
> diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
> index 83d01a9cefc0..55e3aebf4b5e 100644
> --- a/arch/x86/events/intel/uncore.h
> +++ b/arch/x86/events/intel/uncore.h
> @@ -51,6 +51,8 @@ struct uncore_discovery_domain {
>  	/* MSR address or PCI device used as the discovery base */
>  	u32	discovery_base;
>  	bool	base_is_pci;
> +	int	(*global_init)(u64 ctl);
> +
>  	/* The units in the discovery table should be ignored. */
>  	int	*units_ignore;
>  };
> diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/intel/uncore_discovery.c
> index 6f409e0b4722..3a5a3876b74c 100644
> --- a/arch/x86/events/intel/uncore_discovery.c
> +++ b/arch/x86/events/intel/uncore_discovery.c
> @@ -286,6 +286,9 @@ static int __parse_discovery_table(struct uncore_discovery_domain *domain,
>  	if (!io_addr)
>  		return -ENOMEM;
>  
> +	if (domain->global_init && domain->global_init(global.ctl))
> +		return -ENODEV;
> +
>  	/* Parsing Unit Discovery State */
>  	for (i = 0; i < global.max_units; i++) {
>  		memcpy_fromio(&unit, io_addr + (i + 1) * (global.stride * 8),

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