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Message-ID: <469b889f-2497-420e-98ff-b6575d6c5643@linux.intel.com>
Date: Sun, 4 Jan 2026 10:51:20 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: Zide Chen <zide.chen@...el.com>, Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo <acme@...nel.org>,
Namhyung Kim <namhyung@...nel.org>, Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
Xudong Hao <xudong.hao@...el.com>, Falcon Thomas <thomas.falcon@...el.com>
Subject: Re: [PATCH V2 13/13] perf/x86/intel/uncore: Add Nova Lake support
On 1/1/2026 6:42 AM, Zide Chen wrote:
> Nova Lake uncore PMON largely follows Panther Lake and supports CBOX,
> iMC, cNCU, SANTA, sNCU, and HBO units.
>
> As with Panther Lake, CBOX, cNCU, and SANTA are not enumerated via
> discovery tables. Their programming model matches Panther Lake, with
> differences limited to MSR addresses and the number of boxes or counters
> per box.
>
> The remaining units are enumerated via discovery tables using a new
> base MSR (0x711) and otherwise reuse the Panther Lake implementation.
> Nova Lake also supports iMC free-running counters.
>
> Signed-off-by: Zide Chen <zide.chen@...el.com>
> ---
> V2: new patch
>
> arch/x86/events/intel/uncore.c | 9 ++++++
> arch/x86/events/intel/uncore.h | 1 +
> arch/x86/events/intel/uncore_discovery.h | 2 ++
> arch/x86/events/intel/uncore_snb.c | 40 ++++++++++++++++++++++++
> 4 files changed, 52 insertions(+)
>
> diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
> index 07a9a2826398..2607bf178658 100644
> --- a/arch/x86/events/intel/uncore.c
> +++ b/arch/x86/events/intel/uncore.c
> @@ -1817,6 +1817,13 @@ static const struct uncore_plat_init ptl_uncore_init __initconst = {
> .domain[0].global_init = uncore_mmio_global_init,
> };
>
> +static const struct uncore_plat_init nvl_uncore_init __initconst = {
> + .cpu_init = nvl_uncore_cpu_init,
> + .mmio_init = ptl_uncore_mmio_init,
> + .domain[0].discovery_base = PACKAGE_UNCORE_DISCOVERY_MSR,
> + .domain[0].global_init = uncore_mmio_global_init,
> +};
> +
> static const struct uncore_plat_init icx_uncore_init __initconst = {
> .cpu_init = icx_uncore_cpu_init,
> .pci_init = icx_uncore_pci_init,
> @@ -1916,6 +1923,8 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
> X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_uncore_init),
> X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &ptl_uncore_init),
> X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &ptl_uncore_init),
> + X86_MATCH_VFM(INTEL_NOVALAKE, &nvl_uncore_init),
> + X86_MATCH_VFM(INTEL_NOVALAKE_L, &nvl_uncore_init),
> X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &spr_uncore_init),
> X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &spr_uncore_init),
> X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &gnr_uncore_init),
> diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
> index 564cb26c4468..c35918c01afa 100644
> --- a/arch/x86/events/intel/uncore.h
> +++ b/arch/x86/events/intel/uncore.h
> @@ -636,6 +636,7 @@ void adl_uncore_cpu_init(void);
> void lnl_uncore_cpu_init(void);
> void mtl_uncore_cpu_init(void);
> void ptl_uncore_cpu_init(void);
> +void nvl_uncore_cpu_init(void);
> void tgl_uncore_mmio_init(void);
> void tgl_l_uncore_mmio_init(void);
> void adl_uncore_mmio_init(void);
> diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/intel/uncore_discovery.h
> index 63b8f7634e42..e1330342b92e 100644
> --- a/arch/x86/events/intel/uncore_discovery.h
> +++ b/arch/x86/events/intel/uncore_discovery.h
> @@ -4,6 +4,8 @@
> #define UNCORE_DISCOVERY_MSR 0x201e
> /* Base address of uncore perfmon discovery table for CBB domain */
> #define CBB_UNCORE_DISCOVERY_MSR 0x710
> +/* Base address of uncore perfmon discovery table for the package */
> +#define PACKAGE_UNCORE_DISCOVERY_MSR 0x711
>
> /* Generic device ID of a discovery table device */
> #define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7
> diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
> index c663b00b68fe..e8e44741200e 100644
> --- a/arch/x86/events/intel/uncore_snb.c
> +++ b/arch/x86/events/intel/uncore_snb.c
> @@ -256,6 +256,19 @@
> /* PTL cNCU register */
> #define PTL_UNC_CNCU_MSR_OFFSET 0x140
>
> +/* NVL cNCU register */
> +#define NVL_UNC_CNCU_BOX_CTL 0x202e
> +#define NVL_UNC_CNCU_FIXED_CTR 0x2028
> +#define NVL_UNC_CNCU_FIXED_CTRL 0x2022
> +
> +/* NVL SANTA register */
> +#define NVL_UNC_SANTA_CTR0 0x2048
> +#define NVL_UNC_SANTA_CTRL0 0x2042
> +
> +/* NVL CBOX register */
> +#define NVL_UNC_CBOX_PER_CTR0 0x2108
> +#define NVL_UNC_CBOX_PERFEVTSEL0 0x2102
> +
> DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
> DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
> DEFINE_UNCORE_FORMAT_ATTR(chmask, chmask, "config:8-11");
> @@ -1979,3 +1992,30 @@ void ptl_uncore_cpu_init(void)
> }
>
> /* end of Panther Lake uncore support */
> +
> +/* Nova Lake uncore support */
> +
> +static struct intel_uncore_type *nvl_msr_uncores[] = {
> + &mtl_uncore_cbox,
> + &ptl_uncore_santa,
> + &mtl_uncore_cncu,
> + NULL
> +};
> +
> +void nvl_uncore_cpu_init(void)
> +{
> + mtl_uncore_cbox.num_boxes = 12;
> + mtl_uncore_cbox.perf_ctr = NVL_UNC_CBOX_PER_CTR0,
> + mtl_uncore_cbox.event_ctl = NVL_UNC_CBOX_PERFEVTSEL0,
> +
> + ptl_uncore_santa.perf_ctr = NVL_UNC_SANTA_CTR0,
> + ptl_uncore_santa.event_ctl = NVL_UNC_SANTA_CTRL0,
> +
> + mtl_uncore_cncu.box_ctl = NVL_UNC_CNCU_BOX_CTL;
> + mtl_uncore_cncu.fixed_ctr = NVL_UNC_CNCU_FIXED_CTR;
> + mtl_uncore_cncu.fixed_ctl = NVL_UNC_CNCU_FIXED_CTRL;
> +
> + uncore_msr_uncores = nvl_msr_uncores;
> +}
> +
> +/* end of Nova Lake uncore support */
Reviewed-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>
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