linux-kernel - Re: [PATCH 0/2] PCI: endpoint: BAR subrange mapping support

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Message-ID: <aVvtAkEcg6Qg7K3C@ryzen>
Date: Mon, 5 Jan 2026 17:55:30 +0100
From: Niklas Cassel <cassel@...nel.org>
To: Koichiro Den <den@...inux.co.jp>
Cc: jingoohan1@...il.com, mani@...nel.org, lpieralisi@...nel.org,
	kwilczynski@...nel.org, robh@...nel.org, bhelgaas@...gle.com,
	Frank.Li@....com, linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/2] PCI: endpoint: BAR subrange mapping support

Hello Koichiro,

On Mon, Jan 05, 2026 at 05:02:12PM +0900, Koichiro Den wrote:
> This series proposes support for mapping subranges within a PCIe endpoint
> BAR and enables controllers to program inbound address translation for
> those subranges.
> 
> The first patch introduces generic BAR subrange mapping support in the
> PCI endpoint core. The second patch adds an implementation for the
> DesignWare PCIe endpoint controller using Address Match Mode IB iATU.
> 
> This series is a spin-off from a larger RFC series posted earlier:
> https://lore.kernel.org/all/20251217151609.3162665-4-den@valinux.co.jp/
> 
> Base:
>   git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
>   branch: controller/dwc
>   commit: 68ac85fb42cf ("PCI: dwc: Use cfg0_base as iMSI-RX target address
>                          to support 32-bit MSI devices")
> 
> Thank you for reviewing,
> 
> Koichiro Den (2):
>   PCI: endpoint: Add BAR subrange mapping support
>   PCI: dwc: ep: Support BAR subrange inbound mapping via address-match
>     iATU

I have nothing against this feature, but the big question here is:
where is the user?

Usually, we don't add a new feature without having a single user of said
feature.

One thing that I would like to see though:
stricter verification of the pci_epf_bar_submap array.

For DWC, we know that the minimum size that an iATU can map is stored in:
(struct dw_pcie *pci) pci->region_align.

Thus, each element in the pci_epf_bar_submap array has to have a size that
is a multiple of pci->region_align.

I don't see that you ever verify this anywhere.

You should also verify that the sum of all the sizes in the pci_epf_bar_submap
array adds up to exactly pci_epf_bar->size.

Also, we currently have code in dw_pcie_prog_inbound_atu() that verifies
that the physical memory address is aligned to the size of the BAR, as that
is a requirement in BAR match mode, see:
129f6af747b2 ("PCI: dwc: ep: Add 'address' alignment to 'size' check in dw_pcie_prog_ep_inbound_atu()")

This is not a requirement in address match mode, so you probably don't
want to do that check in address match mode.
(You will want to keep the check that the physical memory address is
aligned to pci->region_align though.)

Kind regards,
Niklas