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Message-ID: <f1f2a382-64d9-43dd-bed1-8b1ac9e53470@google.com> Date: Mon, 5 Jan 2026 11:58:29 -0800 From: Amit Sunil Dhamne <amitsd@...gle.com> To: André Draszik <andre.draszik@...aro.org>, Sebastian Reichel <sre@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Lee Jones <lee@...nel.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Badhri Jagan Sridharan <badhri@...gle.com>, Heikki Krogerus <heikki.krogerus@...ux.intel.com>, Peter Griffin <peter.griffin@...aro.org>, Tudor Ambarus <tudor.ambarus@...aro.org>, Alim Akhtar <alim.akhtar@...sung.com> Cc: linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org, devicetree@...r.kernel.org, linux-usb@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org, RD Babiera <rdbabiera@...gle.com>, Kyle Tso <kyletso@...gle.com> Subject: Re: [PATCH v3 3/5] mfd: max77759: add register bitmasks and modify irq configs for charger On 1/5/26 8:45 AM, André Draszik wrote: > On Sat, 2025-12-27 at 00:04 +0000, Amit Sunil Dhamne via B4 Relay wrote: >> From: Amit Sunil Dhamne <amitsd@...gle.com> >> >> Add register bitmasks for charger function. >> In addition split the charger IRQs further such that each bit represents >> an IRQ downstream of charger regmap irq chip. In addition populate the >> ack_base to offload irq ack to the regmap irq chip framework. >> >> Signed-off-by: Amit Sunil Dhamne <amitsd@...gle.com> >> --- >> drivers/mfd/max77759.c | 91 +++++++++++++++++-- >> include/linux/mfd/max77759.h | 202 ++++++++++++++++++++++++++++++++++++------- >> 2 files changed, 256 insertions(+), 37 deletions(-) >> >> [...] >> >> diff --git a/include/linux/mfd/max77759.h b/include/linux/mfd/max77759.h >> index c6face34e385..e674a519e782 100644 >> --- a/include/linux/mfd/max77759.h >> +++ b/include/linux/mfd/max77759.h >> @@ -59,35 +59,65 @@ >> #define MAX77759_MAXQ_REG_AP_DATAIN0 0xb1 >> #define MAX77759_MAXQ_REG_UIC_SWRST 0xe0 >> >> -#define MAX77759_CHGR_REG_CHG_INT 0xb0 >> -#define MAX77759_CHGR_REG_CHG_INT2 0xb1 >> -#define MAX77759_CHGR_REG_CHG_INT_MASK 0xb2 >> -#define MAX77759_CHGR_REG_CHG_INT2_MASK 0xb3 >> -#define MAX77759_CHGR_REG_CHG_INT_OK 0xb4 >> -#define MAX77759_CHGR_REG_CHG_DETAILS_00 0xb5 >> -#define MAX77759_CHGR_REG_CHG_DETAILS_01 0xb6 >> -#define MAX77759_CHGR_REG_CHG_DETAILS_02 0xb7 >> -#define MAX77759_CHGR_REG_CHG_DETAILS_03 0xb8 >> -#define MAX77759_CHGR_REG_CHG_CNFG_00 0xb9 >> -#define MAX77759_CHGR_REG_CHG_CNFG_01 0xba >> -#define MAX77759_CHGR_REG_CHG_CNFG_02 0xbb >> -#define MAX77759_CHGR_REG_CHG_CNFG_03 0xbc >> -#define MAX77759_CHGR_REG_CHG_CNFG_04 0xbd >> -#define MAX77759_CHGR_REG_CHG_CNFG_05 0xbe >> -#define MAX77759_CHGR_REG_CHG_CNFG_06 0xbf >> -#define MAX77759_CHGR_REG_CHG_CNFG_07 0xc0 >> -#define MAX77759_CHGR_REG_CHG_CNFG_08 0xc1 >> -#define MAX77759_CHGR_REG_CHG_CNFG_09 0xc2 >> -#define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3 >> -#define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4 >> -#define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5 >> -#define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6 >> -#define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7 >> -#define MAX77759_CHGR_REG_CHG_CNFG_15 0xc8 >> -#define MAX77759_CHGR_REG_CHG_CNFG_16 0xc9 >> -#define MAX77759_CHGR_REG_CHG_CNFG_17 0xca >> -#define MAX77759_CHGR_REG_CHG_CNFG_18 0xcb >> -#define MAX77759_CHGR_REG_CHG_CNFG_19 0xcc >> +#define MAX77759_CHGR_REG_CHG_INT 0xb0 >> +#define MAX77759_CHGR_REG_CHG_INT_AICL BIT(7) >> +#define MAX77759_CHGR_REG_CHG_INT_CHGIN BIT(6) >> +#define MAX77759_CHGR_REG_CHG_INT_WCIN BIT(5) >> +#define MAX77759_CHGR_REG_CHG_INT_CHG BIT(4) >> +#define MAX77759_CHGR_REG_CHG_INT_BAT BIT(3) >> +#define MAX77759_CHGR_REG_CHG_INT_INLIM BIT(2) >> +#define MAX77759_CHGR_REG_CHG_INT_THM2 BIT(1) >> +#define MAX77759_CHGR_REG_CHG_INT_BYP BIT(0) >> +#define MAX77759_CHGR_REG_CHG_INT2 0xb1 >> +#define MAX77759_CHGR_REG_CHG_INT2_INSEL BIT(7) >> +#define MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1 BIT(6) >> +#define MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2 BIT(5) >> +#define MAX77759_CHGR_REG_CHG_INT2_BAT_OILO BIT(4) >> +#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC BIT(3) >> +#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV BIT(2) >> +#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO BIT(1) >> +#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE BIT(0) >> +#define MAX77759_CHGR_REG_CHG_INT_MASK 0xb2 >> +#define MAX77759_CHGR_REG_CHG_INT2_MASK 0xb3 >> +#define MAX77759_CHGR_REG_CHG_INT_OK 0xb4 >> +#define MAX77759_CHGR_REG_CHG_DETAILS_00 0xb5 >> +#define MAX77759_CHGR_REG_CHG_DETAILS_OO_CHGIN_DTLS GENMASK(6, 5) >> +#define MAX77759_CHGR_REG_CHG_DETAILS_01 0xb6 >> +#define MAX77759_CHGR_REG_CHG_DETAILS_01_BAT_DTLS GENMASK(6, 4) >> +#define MAX77759_CHGR_REG_CHG_DETAILS_01_CHG_DTLS GENMASK(3, 0) >> +#define MAX77759_CHGR_REG_CHG_DETAILS_02 0xb7 >> +#define MAX77759_CHGR_REG_CHG_DETAILS_02_CHGIN_STS BIT(5) >> +#define MAX77759_CHGR_REG_CHG_DETAILS_03 0xb8 >> +#define MAX77759_CHGR_REG_CHG_CNFG_00 0xb9 >> +#define MAX77759_CHGR_REG_CHG_CNFG_00_MODE GENMASK(3, 0) >> +#define MAX77759_CHGR_REG_CHG_CNFG_01 0xba >> +#define MAX77759_CHGR_REG_CHG_CNFG_02 0xbb >> +#define MAX77759_CHGR_REG_CHG_CNFG_02_CHGCC GENMASK(5, 0) > Small nit - there seems to be a stray TAB in this line. Will fix it in the next revision. BR, Amit > > Other than that: > Reviewed-by: André Draszik <andre.draszik@...aro.org>
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