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Message-ID: <819b2f6e5db5411b3ea923bca70482617464594c.camel@ziswiler.com>
Date: Mon, 05 Jan 2026 23:15:29 +0100
From: Marcel Ziswiler <marcel@...wiler.com>
To: Xuyang Dong <dongxuyang@...incomputing.com>, mturquette@...libre.com,
sboyd@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, troy.mitchell@...ux.dev, bmasney@...hat.com
Cc: ningyu@...incomputing.com, linmin@...incomputing.com,
huangyifeng@...incomputing.com, pinkesh.vaghela@...fochips.com,
ganboing@...il.com
Subject: Re: Re: [PATCH v9 2/3] clock: eswin: Add eic7700 clock driver
Hi Xuyang Dong
On Sun, 2026-01-04 at 11:23 +0800, Xuyang Dong wrote:
> > > +
> > > +/* divider clocks */
> > > +static struct eswin_divider_clock eic7700_div_clks[] = {
> > > + EIC7700_DIV(EIC7700_CLK_DIV_SYS_CFG_DYNM, "divider_sys_cfg_div_dynm",
> > > + "fixed_rate_clk_spll0_fout3", 0,
> > > + EIC7700_REG_OFFSET_SYSCFG_CTRL, 4, 3,
> > > + CLK_DIVIDER_ONE_BASED),
> > > + EIC7700_DIV(EIC7700_CLK_DIV_NOC_NSP_DYNM, "divider_noc_nsp_div_dynm",
> > > + "fixed_rate_clk_spll2_fout1", 0,
> > > + EIC7700_REG_OFFSET_NOC_CTRL, 0, 3, CLK_DIVIDER_ONE_BASED),
> > > + EIC7700_DIV(EIC7700_CLK_DIV_BOOTSPI_DYNM, "divider_bootspi_div_dynm",
> > > + "gate_clk_spll0_fout2", 0, EIC7700_REG_OFFSET_BOOTSPI_CTRL,
> > > + 4, 6, CLK_DIVIDER_ONE_BASED),
> > > + EIC7700_DIV(EIC7700_CLK_DIV_SCPU_CORE_DYNM,
> > > + "divider_scpu_core_div_dynm", "fixed_rate_clk_spll0_fout1",
> > > + 0, EIC7700_REG_OFFSET_SCPU_CORE_CTRL, 4, 4,
> > > + CLK_DIVIDER_ONE_BASED),
> > > + EIC7700_DIV(EIC7700_CLK_DIV_LPCPU_CORE_DYNM,
> > > + "divider_lpcpu_core_div_dynm", "fixed_rate_clk_spll0_fout1",
> > > + 0, EIC7700_REG_OFFSET_LPCPU_CORE_CTRL, 4, 4,
> > > + CLK_DIVIDER_ONE_BASED),
> >
> > During testing on top of next-20251219 I got the following:
> >
> > [ 0.126102] divider_lpcpu_core_div_dynm: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
> > [ 0.126194] WARNING: drivers/clk/clk-divider.c:145 at divider_recalc_rate+0x8a/0x9c, CPU#0: swapper/0/1
> >
> > Therefore I suggest for above line needing to be:
> >
> > + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
>
> Hi Marcel,
>
> Thank you! This is indeed a bug and will be fixed in the next version.
> Could you please share the detailed testing methods with me so that I
> can reproduce this issue on my side?
Sure, this was first tested on top of next-20251219, then I re-based it on top of next-20260105 and finally I
ported it to v6.19-rc4 as part of the yocto project integration for the eswin-ebc77-mainline machine [1].
I will further refine this for one of my talks at FOSDEM'26 [2].
Let me know if you have any further questions.
Thanks!
[1] https://github.com/ziswiler/meta-riscv/tree/add-eswin-ebc77-support
[2] https://fosdem.org/2026/schedule/event/LX3NNU-upstream-embedded-linux-on-risc-v-sbcs
> Best regards,
> Xuyang Dong
Cheers
Marcel
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