linux-kernel - Re: [PATCH v2 5/5] KVM: riscv: selftests: add Zilsd and Zclsd extension to get-reg-list test

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Message-ID: <CAAhSdy3OXBexhB_csqJasQoQJ8QnsE=q7dHXgWtyig28eJGL3g@mail.gmail.com>
Date: Mon, 5 Jan 2026 14:36:11 +0530
From: Anup Patel <anup@...infault.org>
To: Pincheng Wang <pincheng.plct@...c.iscas.ac.cn>
Cc: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu, 
	alex@...ti.fr, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, 
	pbonzini@...hat.com, shuah@...nel.org, cyan.yang@...ive.com, 
	cleger@...osinc.com, charlie@...osinc.com, cuiyunhui@...edance.com, 
	samuel.holland@...ive.com, namcao@...utronix.de, jesse@...osinc.com, 
	inochiama@...il.com, yongxuan.wang@...ive.com, ajones@...tanamicro.com, 
	parri.andrea@...il.com, mikisabate@...il.com, yikming2222@...il.com, 
	thomas.weissschuh@...utronix.de, linux-riscv@...ts.infradead.org, 
	linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org, 
	devicetree@...r.kernel.org, kvm@...r.kernel.org, 
	kvm-riscv@...ts.infradead.org, linux-kselftest@...r.kernel.org
Subject: Re: [PATCH v2 5/5] KVM: riscv: selftests: add Zilsd and Zclsd
 extension to get-reg-list test

On Tue, Aug 26, 2025 at 10:00 PM Pincheng Wang
<pincheng.plct@...c.iscas.ac.cn> wrote:
>
> The KVM RISC-V allows Zilsd and Zclsd extensions for Guest/VM so add
> this extension to get-reg-list test.
>
> Signed-off-by: Pincheng Wang <pincheng.plct@...c.iscas.ac.cn>
> ---
>  tools/testing/selftests/kvm/riscv/get-reg-list.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index a0b7dabb5040..477bd386265f 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -78,7 +78,9 @@ bool filter_reg(__u64 reg)
>         case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB:
>         case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD:
>         case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF:
> +       case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCLSD:
>         case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP:
> +       case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZILSD:

KVM_RISCV_ISA_EXT_ZILSD case must be inserted in alphabetical order.

>         case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:
>         case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
>         case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
> @@ -530,7 +532,9 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
>                 KVM_ISA_EXT_ARR(ZCB),
>                 KVM_ISA_EXT_ARR(ZCD),
>                 KVM_ISA_EXT_ARR(ZCF),
> +               KVM_ISA_EXT_ARR(ZCLSD),
>                 KVM_ISA_EXT_ARR(ZCMOP),
> +               KVM_ISA_EXT_ARR(ZILSD),
>                 KVM_ISA_EXT_ARR(ZFA),
>                 KVM_ISA_EXT_ARR(ZFH),
>                 KVM_ISA_EXT_ARR(ZFHMIN),

KVM_ISA_EXT_ARR(ZILSD) must be inserted in alphabetical order.

> @@ -1199,7 +1203,9 @@ struct vcpu_reg_list *vcpu_configs[] = {
>         &config_zcb,
>         &config_zcd,
>         &config_zcf,
> +       &config_zclsd,
>         &config_zcmop,
> +       &config_zclsd,

Both config_zclsd and config_zclsd must be defined before
vcpu_configs[] using KVM_ISA_EXT_SIMPLE_CONFIG().

Also, config_zilsd is not added in alphabetical order.

>         &config_zfa,
>         &config_zfh,
>         &config_zfhmin,
> --
> 2.39.5
>

I have taken care of the above comments at the time of merging.

Reviewed-by: Anup Patel <anup@...infault.org>

Queued this patch for Linux-6.20

Thanks,
Anup