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Message-ID: <CAAhSdy3M8NMF0ojJdoSvtate6FRjS5hno2Wc5i=TeCF84yOK3Q@mail.gmail.com>
Date: Tue, 6 Jan 2026 10:26:34 +0530
From: Anup Patel <anup@...infault.org>
To: Xu Lu <luxu.kernel@...edance.com>
Cc: corbet@....net, paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, alex@...ti.fr, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, will@...nel.org, peterz@...radead.org,
boqun.feng@...il.com, mark.rutland@....com, atish.patra@...ux.dev,
pbonzini@...hat.com, shuah@...nel.org, parri.andrea@...il.com,
ajones@...tanamicro.com, brs@...osinc.com, guoren@...nel.org,
linux-doc@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org, linux-kselftest@...r.kernel.org,
apw@...onical.com, joe@...ches.com, lukas.bulwahn@...il.com
Subject: Re: [PATCH v4 10/10] RISC-V: KVM: selftests: Add Zalasr extensions to
get-reg-list test
On Mon, Oct 20, 2025 at 9:59 AM Xu Lu <luxu.kernel@...edance.com> wrote:
>
> The KVM RISC-V allows Zalasr extensions for Guest/VM so add these
> extensions to get-reg-list test.
>
> Signed-off-by: Xu Lu <luxu.kernel@...edance.com>
LGTM.
Reviewed-by: Anup Patel <anup@...infault.org>
Queued this patch for Linux-6.20
Thanks,
Anup
> ---
> tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index a0b7dabb50406..3020e37f621ba 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -65,6 +65,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAAMO:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS:
> + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALASR:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALRSC:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS:
> case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:
> @@ -517,6 +518,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
> KVM_ISA_EXT_ARR(ZAAMO),
> KVM_ISA_EXT_ARR(ZABHA),
> KVM_ISA_EXT_ARR(ZACAS),
> + KVM_ISA_EXT_ARR(ZALASR),
> KVM_ISA_EXT_ARR(ZALRSC),
> KVM_ISA_EXT_ARR(ZAWRS),
> KVM_ISA_EXT_ARR(ZBA),
> @@ -1112,6 +1114,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(svvptc, SVVPTC);
> KVM_ISA_EXT_SIMPLE_CONFIG(zaamo, ZAAMO);
> KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA);
> KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS);
> +KVM_ISA_EXT_SIMPLE_CONFIG(zalasr, ZALASR);
> KVM_ISA_EXT_SIMPLE_CONFIG(zalrsc, ZALRSC);
> KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS);
> KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
> @@ -1187,6 +1190,7 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &config_zabha,
> &config_zacas,
> &config_zalrsc,
> + &config_zalasr,
> &config_zawrs,
> &config_zba,
> &config_zbb,
> --
> 2.20.1
>
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