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Message-ID: <BL1PR11MB5271B47577A94CE3780D8ABF8C87A@BL1PR11MB5271.namprd11.prod.outlook.com>
Date: Tue, 6 Jan 2026 07:48:50 +0000
From: "Tian, Kevin" <kevin.tian@...el.com>
To: Jason Gunthorpe <jgg@...pe.ca>, Dmytro Maluka <dmaluka@...omium.org>
CC: David Woodhouse <dwmw2@...radead.org>, Lu Baolu
<baolu.lu@...ux.intel.com>, "iommu@...ts.linux.dev" <iommu@...ts.linux.dev>,
Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>, Robin Murphy
<robin.murphy@....com>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "Vineeth Pillai (Google)"
<vineeth@...byteword.org>, Aashish Sharma <aashish@...hishsharma.net>,
Grzegorz Jaszczyk <jaszczyk@...omium.org>, "Dong, Chuanxiao"
<chuanxiao.dong@...el.com>
Subject: RE: [PATCH v2 0/5] iommu/vt-d: Ensure memory ordering in context &
root entry updates
> From: Jason Gunthorpe <jgg@...pe.ca>
> Sent: Tuesday, January 6, 2026 8:14 AM
>
> On Mon, Jan 05, 2026 at 09:05:36PM +0100, Dmytro Maluka wrote:
> > > and WRITE_ONCE is pointless if the HW is promising not to
> > > read it due to non-present.
> >
> > As long as we use a barrier. And IIUC vice versa, if we use WRITE_ONCE
> > for any updates, a barrier is not necessary (on x86). And WRITE_ONCE for
> > any updates (for PASID entries) is what was already done before this
> > series.
>
> That is an x86 ism and it shouldn't be needlessly leaked into drivers.
yeah WRITE_ONCE() is not by definition to guarantee the ordering between
CPU and device.
lots of READ_ONCE()/WRITE_ONCE() in existing code are meaningless,
as 1) between CPUs there is already lock protection; 2) between CPU and
device it requires dma_wmb() to guarantee the order.
> As this is not performance it should have the portable flow:
>
> WRITE_ONCE(non-present)
> dma_wmb()
> <cmd to flush caches>
>
> [..]
> <writes to the entry>
>
> dma_wmb()
> WRITE_ONCE(present)
>
> So, it seems to me like all you need here is the one line to add the
> dma_wmb() prior to setting present.
+1
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