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Message-ID: <20260106092117.3727152-4-joshua.yeong@starfivetech.com>
Date: Tue, 6 Jan 2026 17:21:14 +0800
From: Joshua Yeong <joshua.yeong@...rfivetech.com>
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Subject: [PATCH 3/5] dt-bindings: riscv: cpus: document performance-domains property
The property is defined as a phandle array referencing an RPMI
performance domain provider, with the domain specifier interpreted
according to the bindings of the referenced RPMI performance controller.
Signed-off-by: Joshua Yeong <joshua.yeong@...rfivetech.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d733c0bd534f..a7c38d078981 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -143,6 +143,13 @@ properties:
DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system.
+ performance-domains:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ A phandle and RPMI performance domain specifier, as defined by the
+ bindings of the referenced RPMI performance controller or provider.
+ (see riscv,rpmi-performance.yaml / riscv,rpmi-mpxy-performance.yaml)
+
anyOf:
- required:
- riscv,isa
--
2.43.0
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