linux-kernel - Re: [PATCH v3 0/4] PCI: dwc: Rework the error handling of dw_pcie_wait_for

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <aV5XI_e3npXHsxk7@ryzen>
Date: Wed, 7 Jan 2026 13:52:51 +0100
From: Niklas Cassel <cassel@...nel.org>
To: Manivannan Sadhasivam <mani@...nel.org>
Cc: manivannan.sadhasivam@....qualcomm.com,
	Jingoo Han <jingoohan1@...il.com>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kwilczynski@...nel.org>,
	Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
	linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
	vincent.guittot@...aro.org, zhangsenchuan@...incomputing.com,
	Shawn Lin <shawn.lin@...k-chips.com>, dlemoal@...nel.org
Subject: Re: [PATCH v3 0/4] PCI: dwc: Rework the error handling of
 dw_pcie_wait_for_link() API

On Mon, Jan 05, 2026 at 05:11:42PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Jan 02, 2026 at 01:01:02PM +0100, Niklas Cassel wrote:
> > On Tue, Dec 30, 2025 at 08:37:31PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> 
> What could be happening here is that since the endpoint is physically connected
> to the bus, the receiver gets detected during Detect.Active state and LTSSM
> enters the Polling state. I think the reason why it ended up staying in
> Poll.Compliance could be due to (as per the spec):
> 
> a. Not all Lanes from the predetermined set of Lanes from above have
> detected an exit from Electrical Idle since entering Polling.Active.
> 
> b. Any Lane that detected a Receiver during Detect received eight consecutive
> TS1 Ordered Sets (or their complement) with the Lane and Link numbers set to
> PAD, the Compliance Receive bit (bit 4 of Symbol 5) is 1b, and the Loopback bit
> (bit 2 of Symbol 5) is 0b that the Compliance Receive bit (bit 4 of Symbol 5) is
> set.
> 
> So this is perfectly legal from endpoint perspective.
> 
> > Perhaps a Kconfig or module param? Suggestions?
> > 
> 
> There is a DIRECT_POLCOMP_TO_DETECT bit (bit 9) in DBI SD_CONTROL2 register.
> This bit will ensure that the LTSSM will not stuck in Poll.Compliance and will
> return back to Detect state. Could you set it on the EP before starting LTSSM
> and see if it helps?

I will test and get back to you.


Kind regards,
Niklas