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Message-ID: <a72faee7-b77f-4654-aab3-8fe24472aaac@redhat.com>
Date: Wed, 7 Jan 2026 20:18:42 +0100
From: Ivan Vecera <ivecera@...hat.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Rob Herring <robh@...nel.org>, netdev@...r.kernel.org,
Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Vadim Fedorenko <vadim.fedorenko@...ux.dev>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>,
Grzegorz Nitka <grzegorz.nitka@...el.com>, Jiri Pirko <jiri@...nulli.us>,
Petr Oros <poros@...hat.com>, Michal Schmidt <mschmidt@...hat.com>,
Prathosh Satish <Prathosh.Satish@...rochip.com>,
Tony Nguyen <anthony.l.nguyen@...el.com>,
Przemek Kitszel <przemyslaw.kitszel@...el.com>,
Saeed Mahameed <saeedm@...dia.com>, Leon Romanovsky <leon@...nel.org>,
Tariq Toukan <tariqt@...dia.com>, Mark Bloch <mbloch@...dia.com>,
Richard Cochran <richardcochran@...il.com>,
Jonathan Lemon <jonathan.lemon@...il.com>, Simon Horman <horms@...nel.org>,
Alexander Lobakin <aleksander.lobakin@...el.com>,
Willem de Bruijn <willemb@...gle.com>, Stefan Wahren <wahrenst@....net>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
intel-wired-lan@...ts.osuosl.org, linux-rdma@...r.kernel.org,
Horatiu Vultur <Horatiu.Vultur@...rochip.com>
Subject: Re: [PATCH RFC net-next 01/13] dt-bindings: net: ethernet-controller:
Add DPLL pin properties
On 1/7/26 6:31 PM, Andrew Lunn wrote:
>>> I have no idea what makes sense for ACPI and little interest in
>>> reviewing ACPI bindings. While I think the whole idea of shared
>>> bindings is questionable, really it's a question of review bandwidth
>>> and so far no one has stepped up to review ACPI bindings.
>>
>> It depends... shared bindings allow drivers to read property values
>> without need to have separate OF and ACPI codepaths.
>
> Do you have real hardware in your hands using ACPI?
>
Yes, it is based on Intel GNR-D platform with 8 NIC ports and Microchip
DPLL chip on the board.
I.
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