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Message-ID: <9730440b-b4ef-4b9a-ac77-37945c5b4f5c@oss.qualcomm.com>
Date: Wed, 7 Jan 2026 10:47:14 +0800
From: Wenmeng Liu <wenmeng.liu@....qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Cc: Loic Poulain <loic.poulain@....qualcomm.com>,
Robert Foss <rfoss@...nel.org>, Andi Shyti <andi.shyti@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Todor Tomov <todor.too@...il.com>,
Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>,
linux-i2c@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-media@...r.kernel.org
Subject: Re: [PATCH v2 2/4] arm64: dts: qcom: talos: Add CCI definitions
On 1/7/2026 2:27 AM, Dmitry Baryshkov wrote:
> On Tue, Jan 06, 2026 at 05:39:54PM +0800, Wenmeng Liu wrote:
>> Qualcomm Talos SoC contains single controller,
>> containing 2 I2C hosts.
>>
>> Signed-off-by: Wenmeng Liu <wenmeng.liu@....qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/talos.dtsi | 72 +++++++++++++++++++++++++++++++++++++
>> 1 file changed, 72 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
>> index e1dfaff9b6bf8641b19a685e74d60ad4e1e99d41..461a39968d928260828993ff3549aa15fd1870df 100644
>> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
>> @@ -1549,6 +1549,42 @@ tlmm: pinctrl@...0000 {
>> #interrupt-cells = <2>;
>> wakeup-parent = <&pdc>;
>>
>> + cci_default: cci0-default-state {
>> + cci_i2c0_default: cci-i2c0-default-pins {
>
> These need to be split, having just one host per state.
ACK.>
>> + /* SDA, SCL */
>> + pins = "gpio32", "gpio33";
>> + function = "cci_i2c";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> +
>> + cci_i2c1_default: cci-i2c1-default-pins {
>> + /* SDA, SCL */
>> + pins = "gpio34", "gpio35";
>> + function = "cci_i2c";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + cci_sleep: cci-sleep-state {
>> + cci_i2c0_sleep: cci-i2c0-sleep-state {
>
> The same
ACK.>
>> + /* SDA, SCL */
>> + pins = "gpio32", "gpio33";
>> + function = "cci_i2c";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + cci_i2c1_sleep: cci-i2c1-sleep-state {
>> + /* SDA, SCL */
>> + pins = "gpio34", "gpio35";
>> + function = "cci_i2c";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> + };
>> +
>> qup_i2c1_data_clk: qup-i2c1-data-clk-state {
>> pins = "gpio4", "gpio5";
>> function = "qup0";
>> @@ -3785,6 +3821,42 @@ videocc: clock-controller@...0000 {
>> #power-domain-cells = <1>;
>> };
>>
>> + cci: cci@...a000 {
>> + compatible = "qcom,sm6150-cci", "qcom,msm8996-cci";
>> +
>> + reg = <0x0 0x0ac4a000 0x0 0x4000>;
>
> Extra double space.
ACK.>
>> + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
>> + power-domains = <&camcc TITAN_TOP_GDSC>;
>> + clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
>> + <&camcc CAM_CC_CPAS_AHB_CLK>,
>> + <&camcc CAM_CC_CCI_CLK>;
>> + clock-names = "soc_ahb",
>> + "cpas_ahb",
>> + "cci";
>> + pinctrl-0 = <&cci_default>;
>> + pinctrl-1 = <&cci_sleep>;
>> + pinctrl-names = "default", "sleep";
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + status = "disabled";
>> +
>> + cci_i2c0: i2c-bus@0 {
>> + reg = <0>;
>> + clock-frequency = <1000000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + cci_i2c1: i2c-bus@1 {
>> + reg = <1>;
>> + clock-frequency = <1000000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> + };
>> +
>> camss: isp@...3000 {
>> compatible = "qcom,sm6150-camss";
>>
>>
>> --
>> 2.34.1
>>
>
Will fix in next version.
Thanks,
Wenmeng
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