lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <245bb0d1cfc1dee91baaab7c1fd73bc264586a0d.camel@codeconstruct.com.au>
Date: Thu, 08 Jan 2026 10:14:17 +1030
From: Andrew Jeffery <andrew@...econstruct.com.au>
To: Billy Tsai <billy_tsai@...eedtech.com>, Tony Lindgren
 <tony@...mide.com>,  Haojian Zhuang <haojian.zhuang@...aro.org>, Linus
 Walleij <linusw@...nel.org>
Cc: linux-arm-kernel@...ts.infradead.org, linux-omap@...r.kernel.org, 
	linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
 BMC-SW@...eedtech.com
Subject: Re: [PATCH 0/3] pinctrl: single: bit-per-mux DT flexibility, probe
 robustness, and consistent pinconf offsets

Hi Billy,

On Mon, 2025-12-22 at 20:04 +0800, Billy Tsai wrote:
> This series updates pinctrl-single to behave more predictably on
> bit-per-mux platforms by making its DT interface more flexible, its probe
> path more tolerant of pre-reserved resources, and its pin configuration
> register addressing consistent with pinmux.

Can you provide some more context here? For instance, this is motivated
by the AST2700 - can you talk a bit more about why its design needs
these changes?

> It extends the driver to accept a per-pin <pin_index func_sel> style
> description for bit-per-mux users while keeping the existing
> pinctrl-single,bits binding as the preferred input when available. It also
> relaxes probe failure when the I/O memory region cannot be reserved
> exclusively, allowing initialization to proceed with a warning on systems
> where that region is already reserved.
> 

Can you unpack what's going on here in the context of the target soc?

Andrew

>  Finally, it aligns pinconf register
> offset computation with the pinmux logic so that both muxing and pin
> configuration access the same register offsets, avoiding incorrect pinconf
> operations on bit-per-mux configurations.
> 
> Signed-off-by: Billy Tsai <billy_tsai@...eedtech.com>
> ---
> Billy Tsai (3):
>       pinctrl: single: add per-pin binding support for bit-per-mux
>       pinctrl: single: Allow probe to continue if mem region busy
>       pinctrl: single: unify pinconf offset mapping with pinmux
> 
>  drivers/pinctrl/pinctrl-single.c | 150 ++++++++++++++++++++++++++++-----------
>  1 file changed, 110 insertions(+), 40 deletions(-)
> ---
> base-commit: dd9b004b7ff3289fb7bae35130c0a5c0537266af
> change-id: 20251222-upstream_pinctrl_single-99e8df1fe2b9
> 
> Best regards,

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ