linux-kernel - Re: [PATCH v7 3/4] clk: samsung: Implement automatic clock gating mode for CMUs

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Message-ID: <39019203631fdd183fb5ddaa7fada5da5f2a31ad.camel@linaro.org>
Date: Wed, 07 Jan 2026 07:22:44 +0000
From: André Draszik <andre.draszik@...aro.org>
To: Peter Griffin <peter.griffin@...aro.org>, Krzysztof Kozlowski	
 <krzk+dt@...nel.org>, Alim Akhtar <alim.akhtar@...sung.com>, Tudor Ambarus	
 <tudor.ambarus@...aro.org>, Michael Turquette <mturquette@...libre.com>, 
 Stephen Boyd <sboyd@...nel.org>, Sam Protsenko
 <semen.protsenko@...aro.org>, Sylwester Nawrocki	 <s.nawrocki@...sung.com>,
 Chanwoo Choi <cw00.choi@...sung.com>
Cc: Will McVicker <willmcvicker@...gle.com>, Krzysztof Kozlowski	
 <krzk@...nel.org>, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
 kernel-team@...roid.com,  Rob Herring <robh@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>
Subject: Re: [PATCH v7 3/4] clk: samsung: Implement automatic clock gating
 mode for CMUs

Hi,

On Mon, 2025-12-22 at 10:22 +0000, Peter Griffin wrote:
> Update exynos_arm64_init_clocks() so that it enables the automatic clock
> mode bits in the CMU option register if the auto_clock_gate flag and
> option_offset fields are set for the CMU. To ensure compatibility with
> older DTs (that specified an incorrect CMU reg size), detect this and
> fallback to manual clock gate mode as the auto clock mode feature depends
> on registers in this area.
> 
> The CMU option register bits are global and effect every clock component in
> the CMU, as such clearing the GATE_ENABLE_HWACG bit and setting GATE_MANUAL
> bit on every gate register is only required if auto_clock_gate is false.
> 
> Additionally if auto_clock_gate is enabled the dynamic root clock gating
> and memclk registers will be configured in the corresponding CMUs sysreg
> bank. These registers are exposed via syscon, so the register
> samsung_clk_save/restore paths are updated to also take a regmap.

The implementation described in this paragraph this causes pm-runtime to
stop working for the CMU if auto clock gating is enabled.

See below.

> [...]
> diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
> index c149ca6c221725195faeb76b0d73374c3b48261b..06ea5deef4ee2ffb87dcd14102561886ea80b7bc 100644
> --- a/drivers/clk/samsung/clk.c
> +++ b/drivers/clk/samsung/clk.c
> [...]
> @@ -357,6 +489,37 @@ void __init samsung_cmu_register_clocks(struct samsung_clk_provider *ctx,
>  		samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks);
>  }
>  
> +/* Each bit enable/disables DRCG of a bus component */
> +#define DRCG_EN_MSK	GENMASK(31, 0)
> +#define MEMCLK_EN	BIT(0)
> +
> +/* Enable Dynamic Root Clock Gating (DRCG) of bus components */
> +void samsung_en_dyn_root_clk_gating(struct device_node *np,
> +				    struct samsung_clk_provider *ctx,
> +				    const struct samsung_cmu_info *cmu)
> +{
> +	if (!ctx->auto_clock_gate)
> +		return;
> +
> +	ctx->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg");

With this, the CMU driver (e.g. cmu_hsi0) now gets a reference to the respective
sysreg (sysreg_hsi0), which in turn creates a regmap with a clock handle
(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK), and the clock is 'prepared'. Hence the CMU
providing this clock (cmu_hsi0) is not idle anymore, and runtime PM for this
CMU can't kick in anymore

I see two straight forward options to fix this:

1) The easiest fix is to just drop the clock from the sysreg DT node. The sysreg
clock shouldn't matter now, as the whole CMU is in auto mode now anyway.

2) change above code to use device_node_to_regmap() which ignores resources (the
sysreg clock in the example case), and manage the clock manually during save and
restore in samsung_clk_save() and samsung_clk_restore()

Any better ideas?


Cheers,
Andre'