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Message-ID: <CAPYmKFscKJ1ff470d6YmuMxLdJPSZ-ZmuGMMAFO83TT-vvV2JQ@mail.gmail.com>
Date: Wed, 7 Jan 2026 18:01:26 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: Andrew Jones <ajones@...tanamicro.com>
Cc: Jason Gunthorpe <jgg@...dia.com>, Zong Li <zong.li@...ive.com>, 
	Tomasz Jeznach <tjeznach@...osinc.com>, joro@...tes.org, Will Deacon <will@...nel.org>, 
	Robin Murphy <robin.murphy@....com>, Anup Patel <anup@...infault.org>, atish.patra@...ux.dev, 
	Thomas Gleixner <tglx@...utronix.de>, alex.williamson@...hat.com, 
	Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, 
	Alexandre Ghiti <alex@...ti.fr>, iommu@...ts.linux.dev, kvm-riscv@...ts.infradead.org, 
	kvm@...r.kernel.org, linux-riscv <linux-riscv@...ts.infradead.org>, 
	LKML <linux-kernel@...r.kernel.org>
Subject: Question about RISCV IOMMU irqbypass patch series

Hi Andrew,

Thanks for your brilliant job on the RISCV IOMMU irqbypass patch
series[1]. I have rebased it on v6.18 and successfully passed through
a nvme device to VM. But I still have some questions about it.

1. It seems "irqdomain->host_data->domain" can be NULL for blocking or
identity domain. So it's better to check whether it's NULL in
riscv_iommu_ir_irq_domain_alloc_irqs or
riscv_iommu_ir_irq_domain_free_irqs functions. Otherwise page fault
can happen.

2. It seems you are using the first stage iommu page table even for
gpa->spa, what if a VM needs an vIOMMU? Or did I miss something?

[1] https://lore.kernel.org/all/20250920203851.2205115-20-ajones@ventanamicro.com/

Best regards,
Xu Lu

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