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Message-ID: <176788711595.3235249.5659814329200289480.b4-ty@sntech.de>
Date: Thu, 8 Jan 2026 16:45:19 +0100
From: Heiko Stuebner <heiko@...ech.de>
To: Andy Yan <andyshrk@....com>
Cc: Heiko Stuebner <heiko@...ech.de>,
hjc@...k-chips.com,
dri-devel@...ts.freedesktop.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-rockchip@...ts.infradead.org,
Andy Yan <andy.yan@...k-chips.com>
Subject: Re: [PATCH 1/2] drm/rockchip: vop2: Add delay between poll registers
On Fri, 18 Jul 2025 14:41:13 +0800, Andy Yan wrote:
> According to the implementation of read_poll_timeout_atomic, if the
> delay time is 0, it will only use a simple loop based on timeout_us to
> decrement the count. Therefore, the final timeout time will differ
> significantly from the setted timteout time. So, here we set a specific
> delay time to ensure that the calculation of the timeout duration is accurate.
>
>
> [...]
Applied, thanks!
[1/2] drm/rockchip: vop2: Add delay between poll registers
commit: 9fae82450d8a5f9c8fa016cd15186e975609b2ac
[2/2] drm/rockchip: vop2: Only wait for changed layer cfg done when there is pending cfgdone bits
commit: 7f6721b767e219343cfe9a894f5bd869ff5b9d3a
Best regards,
--
Heiko Stuebner <heiko@...ech.de>
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