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Message-ID: <20260108165414.GF23056@nvidia.com>
Date: Thu, 8 Jan 2026 12:54:14 -0400
From: Jason Gunthorpe <jgg@...dia.com>
To: Robin Murphy <robin.murphy@....com>
Cc: Will Deacon <will@...nel.org>, Marc Zyngier <maz@...nel.org>,
	Lucas Wei <lucaswei@...gle.com>,
	Catalin Marinas <catalin.marinas@....com>,
	Jonathan Corbet <corbet@....net>, sjadavani@...gle.com,
	kernel test robot <lkp@...el.com>, stable@...r.kernel.org,
	kernel-team@...roid.com, linux-arm-kernel@...ts.infradead.org,
	linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
	smostafa@...gle.com
Subject: Re: [PATCH v2] arm64: errata: Workaround for SI L1 downstream
 coherency issue

On Thu, Jan 08, 2026 at 04:41:47PM +0000, Robin Murphy wrote:

> The point is that if there's a coherent interconnect downstream of the SMMU
> - which we infer from the SMMU's own coherency - then we should be able to
> make the *output* of SMMU translation coherent,

Sadly I'm aware of HW where that isn't true..

The SMMU is flexible and there are more than one fabric connection
from a SW visible SMMU instance. They can have different properties.

Especially if the design is focused on something like isochronous real
time guarentees.

Jason

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