linux-kernel - Re: [PATCH v2 1/5] clk: qcom: cmnpll: Account for reference clock divider

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Message-ID: <b132680b-5e85-4239-a42f-f6e79471486b@oss.qualcomm.com>
Date: Thu, 8 Jan 2026 14:39:59 +0800
From: Jie Luo <jie.luo@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd
 <sboyd@...nel.org>, Luo Jie <quic_luoj@...cinc.com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        quic_kkumarcs@...cinc.com, quic_linchen@...cinc.com,
        quic_leiwei@...cinc.com, quic_pavir@...cinc.com,
        quic_suruchia@...cinc.com
Subject: Re: [PATCH v2 1/5] clk: qcom: cmnpll: Account for reference clock
 divider



On 1/7/2026 8:16 PM, Konrad Dybcio wrote:
> On 1/7/26 6:35 AM, Luo Jie wrote:
>> The clk_cmn_pll_recalc_rate() function must account for the reference clock
>> divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
>> with a reference divider other than 1 calculate incorrect CMN PLL rates.
>> For example, on IPQ5332 where the reference divider is 2, the computed rate
>> becomes twice the actual output.
>>
>> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
>> applying the 2 * FACTOR scaling. This yields the correct rate calculation:
>> rate = (parent_rate / ref_div) * 2 * factor.
>>
>> Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
>> IPQ5424, IPQ5018) that use ref_div = 1.
>>
>> Fixes: f81715a4c87c ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC")
>> Signed-off-by: Luo Jie <jie.luo@....qualcomm.com>
>> ---
>>  drivers/clk/qcom/ipq-cmn-pll.c | 11 +++++++++--
>>  1 file changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c
>> index dafbf5732048..369798d1ce42 100644
>> --- a/drivers/clk/qcom/ipq-cmn-pll.c
>> +++ b/drivers/clk/qcom/ipq-cmn-pll.c
>> @@ -185,7 +185,7 @@ static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw,
>>  					     unsigned long parent_rate)
>>  {
>>  	struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw);
>> -	u32 val, factor;
>> +	u32 val, factor, ref_div;
>>  
>>  	/*
>>  	 * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted
>> @@ -193,8 +193,15 @@ static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw,
>>  	 */
>>  	regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val);
>>  	factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val);
>> +	if (WARN_ON(factor == 0))
>> +		factor = 1;
> 
> FWIW the docs tell me the value of this field is '192' on IPQ5332..
> 
> Konrad

Although the register description lists the default value as 192, the
actual runtime value is 125 on IPQ5332, as shown in the dump below.

# devmem 0x9B794
0x00006C7D

# cat /sys/kernel/debug/clk/clk_summary | grep cmn_pll -B 2
 xo-clk                              1       1        0        48000000
  0          0     50000      Y   deviceless
no_connection_id
    ref-48mhz-clk                    2       2        0        48000000
  0          0     50000      Y      deviceless
no_connection_id
       cmn_pll                       3       3        0
6000000000  0          0     50000      Y         deviceless
         no_connection_id