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Message-Id: <20260109-apple-dt-usb-c-atc-dwc3-v1-2-ce0e92c1a016@jannau.net>
Date: Fri, 09 Jan 2026 15:07:05 +0100
From: Janne Grunau <j@...nau.net>
To: Sven Peter <sven@...nel.org>, Neal Gompa <neal@...pa.dev>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: asahi@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Janne Grunau <j@...nau.net>, Hector Martin <marcan@...can.st>
Subject: [PATCH 2/3] arm64: dts: apple: t8112: Add nodes for integrated USB
Type-C ports
From: Hector Martin <marcan@...can.st>
Add device nodes and connections to support USB 3.x on the SoC's
integrated USBi Type-C ports of M2-based devices.
Each Type-C port has an Apple Type-C PHY for USB 2.0, USB 3.x,
USB4/Thunderbolt, and DisplayPort, a Synopsys Designware USB 3.x
controller, two DART iommu instances and a CD321x USB PD controller.
The port labels use Apple's established naming scheme for the ports.
Signed-off-by: Hector Martin <marcan@...can.st>
Co-developed-by: Janne Grunau <j@...nau.net>
Signed-off-by: Janne Grunau <j@...nau.net>
---
arch/arm64/boot/dts/apple/t8112-j413.dts | 12 +++
arch/arm64/boot/dts/apple/t8112-j415.dts | 12 +++
arch/arm64/boot/dts/apple/t8112-j473.dts | 12 +++
arch/arm64/boot/dts/apple/t8112-j493.dts | 12 +++
arch/arm64/boot/dts/apple/t8112-jxxx.dtsi | 134 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/apple/t8112.dtsi | 105 +++++++++++++++++++++++
6 files changed, 287 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8112-j413.dts b/arch/arm64/boot/dts/apple/t8112-j413.dts
index 6f69658623bf89ce73e3486bce504f1f5f8003f3..21e81a8899d8d7ff5461db085b53feccc7c53f64 100644
--- a/arch/arm64/boot/dts/apple/t8112-j413.dts
+++ b/arch/arm64/boot/dts/apple/t8112-j413.dts
@@ -60,6 +60,18 @@ bluetooth0: bluetooth@0,1 {
};
};
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Left-back";
+};
+
+&typec1 {
+ label = "USB-C Left-front";
+};
+
&i2c0 {
/* MagSafe port */
hpm5: usb-pd@3a {
diff --git a/arch/arm64/boot/dts/apple/t8112-j415.dts b/arch/arm64/boot/dts/apple/t8112-j415.dts
index b54e218e5384ca89155e4350d6680a28a531f408..b4f72fbafaf104573c86ceff9283c05d43aee080 100644
--- a/arch/arm64/boot/dts/apple/t8112-j415.dts
+++ b/arch/arm64/boot/dts/apple/t8112-j415.dts
@@ -60,6 +60,18 @@ bluetooth0: bluetooth@0,1 {
};
};
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Left-back";
+};
+
+&typec1 {
+ label = "USB-C Left-front";
+};
+
&i2c0 {
/* MagSafe port */
hpm5: usb-pd@3a {
diff --git a/arch/arm64/boot/dts/apple/t8112-j473.dts b/arch/arm64/boot/dts/apple/t8112-j473.dts
index 06fe257f08be498ace6906b936012e01084da702..81994f0a7df962d982b675deb4c35b25fa3c29f6 100644
--- a/arch/arm64/boot/dts/apple/t8112-j473.dts
+++ b/arch/arm64/boot/dts/apple/t8112-j473.dts
@@ -52,3 +52,15 @@ &pcie1_dart {
&pcie2_dart {
status = "okay";
};
+
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Back-left";
+};
+
+&typec1 {
+ label = "USB-C Back-right";
+};
diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts/apple/t8112-j493.dts
index fb8ad7d4c65a8fe7966f5541f24f03a379143cfb..f8e442152ff23f21a46916ac111e5f6bbc87cf83 100644
--- a/arch/arm64/boot/dts/apple/t8112-j493.dts
+++ b/arch/arm64/boot/dts/apple/t8112-j493.dts
@@ -108,6 +108,18 @@ bluetooth0: bluetooth@0,1 {
};
};
+/*
+ * Provide labels for the USB type C ports.
+ */
+
+&typec0 {
+ label = "USB-C Left-back";
+};
+
+&typec1 {
+ label = "USB-C Left-front";
+};
+
&i2c4 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi
index 6da35496a4c88dbaba125ebbe8c5a4a428c647c3..562e7a25a1e8843f516c3d7327254049332cd08d 100644
--- a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi
+++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi
@@ -11,6 +11,8 @@
/ {
aliases {
+ atcphy0 = &atcphy0;
+ atcphy1 = &atcphy1;
serial0 = &serial0;
serial2 = &serial2;
};
@@ -53,6 +55,29 @@ hpm0: usb-pd@38 {
interrupt-parent = <&pinctrl_ap>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec0: connector {
+ compatible = "usb-c-connector";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec0_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_0_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec0_connector_ss: endpoint {
+ remote-endpoint = <&atcphy0_typec_lanes>;
+ };
+ };
+ };
+ };
};
hpm1: usb-pd@3f {
@@ -61,6 +86,115 @@ hpm1: usb-pd@3f {
interrupt-parent = <&pinctrl_ap>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "irq";
+
+ typec1: connector {
+ compatible = "usb-c-connector";
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec1_connector_hs: endpoint {
+ remote-endpoint = <&dwc3_1_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec1_connector_ss: endpoint {
+ remote-endpoint = <&atcphy1_typec_lanes>;
+ };
+ };
+ };
+ };
+ };
+};
+
+/* USB controllers */
+&dwc3_0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_0_hs: endpoint {
+ remote-endpoint = <&typec0_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_0_ss: endpoint {
+ remote-endpoint = <&atcphy0_usb3>;
+ };
+ };
+ };
+};
+
+&dwc3_1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dwc3_1_hs: endpoint {
+ remote-endpoint = <&typec1_connector_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dwc3_1_ss: endpoint {
+ remote-endpoint = <&atcphy1_usb3>;
+ };
+ };
+ };
+};
+
+/* Type-C PHYs */
+&atcphy0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy0_typec_lanes: endpoint {
+ remote-endpoint = <&typec0_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy0_usb3: endpoint {
+ remote-endpoint = <&dwc3_0_ss>;
+ };
+ };
+ };
+};
+
+&atcphy1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ atcphy1_typec_lanes: endpoint {
+ remote-endpoint = <&typec1_connector_ss>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ atcphy1_usb3: endpoint {
+ remote-endpoint = <&dwc3_1_ss>;
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi
index 3f79878b25af1f7760088aa552589494d67347fb..2d645cdec4a75fcfe1897d42f9af460e2752f2eb 100644
--- a/arch/arm64/boot/dts/apple/t8112.dtsi
+++ b/arch/arm64/boot/dts/apple/t8112.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/spmi/spmi.h>
/ {
@@ -1010,6 +1011,110 @@ nvme@...cc0000 {
resets = <&ps_ans>;
};
+ dwc3_0: usb@...280000 {
+ compatible = "apple,t8112-dwc3", "apple,t8103-dwc3";
+ reg = <0x3 0x82280000 0x0 0xcd00>, <0x3 0x8228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1031 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>;
+ power-domains = <&ps_atc0_usb>;
+ resets = <&atcphy0>;
+ phys = <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ dwc3_0_dart_0: iommu@...f00000 {
+ compatible = "apple,t8110-dart";
+ reg = <0x3 0x82f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1035 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc0_usb>;
+ };
+
+ dwc3_0_dart_1: iommu@...f80000 {
+ compatible = "apple,t8110-dart";
+ reg = <0x3 0x82f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1035 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc0_usb>;
+ };
+
+ atcphy0: phy@...000000 {
+ compatible = "apple,t8112-atcphy", "apple,t8103-atcphy";
+ reg = <0x3 0x83000000 0x0 0x4c000>,
+ <0x3 0x83050000 0x0 0x8000>,
+ <0x3 0x80000000 0x0 0x4000>,
+ <0x3 0x82a90000 0x0 0x4000>,
+ <0x3 0x82a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&ps_atc0_usb>;
+ };
+
+ dwc3_1: usb@...280000 {
+ compatible = "apple,t8112-dwc3", "apple,t8103-dwc3";
+ reg = <0x5 0x02280000 0x0 0xcd00>, <0x5 0x0228cd00 0x0 0x3200>;
+ reg-names = "dwc3-core", "dwc3-apple";
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1112 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "host";
+ iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>;
+ power-domains = <&ps_atc1_usb>;
+ resets = <&atcphy1>;
+ phys = <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ dwc3_1_dart_0: iommu@...f00000 {
+ compatible = "apple,t8110-dart";
+ reg = <0x5 0x02f00000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1116 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc1_usb>;
+ };
+
+ dwc3_1_dart_1: iommu@...f80000 {
+ compatible = "apple,t8110-dart";
+ reg = <0x5 0x02f80000 0x0 0x4000>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 1116 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ power-domains = <&ps_atc1_usb>;
+ };
+
+ atcphy1: phy@...000000 {
+ compatible = "apple,t8112-atcphy", "apple,t8103-atcphy";
+ reg = <0x5 0x03000000 0x0 0x4c000>,
+ <0x5 0x03050000 0x0 0x8000>,
+ <0x5 0x0 0x0 0x4000>,
+ <0x5 0x02a90000 0x0 0x4000>,
+ <0x5 0x02a84000 0x0 0x4000>;
+ reg-names = "core", "lpdptx", "axi2af", "usb2phy",
+ "pipehandler";
+
+ #phy-cells = <1>;
+ #reset-cells = <0>;
+
+ orientation-switch;
+ mode-switch;
+ power-domains = <&ps_atc1_usb>;
+ };
+
pcie0_dart: iommu@...008000 {
compatible = "apple,t8110-dart";
reg = <0x6 0x81008000 0x0 0x4000>;
--
2.52.0
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