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Message-Id: <20260109-clk-samsung-autoclk-updates-v1-3-2394dcf242a9@linaro.org>
Date: Fri, 09 Jan 2026 17:27:25 +0000
From: André Draszik <andre.draszik@...aro.org>
To: Krzysztof Kozlowski <krzk@...nel.org>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
Cc: Peter Griffin <peter.griffin@...aro.org>,
Tudor Ambarus <tudor.ambarus@...aro.org>,
Will McVicker <willmcvicker@...gle.com>, Juan Yescas <jyescas@...gle.com>,
linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
André Draszik <andre.draszik@...aro.org>
Subject: [PATCH 3/3] clk: samsung: allow runtime PM with auto clock gating
When automatic clock gating is enabled, runtime PM (RPM) isn't entered
even if enabled for a CMU if a sysreg clock exists and is provided by
this CMU (as is generally the case).
The reason is that this driver acquires a CMU's sysreg registers using
syscon_regmap_lookup_by_phandle() which ends up preparing the sysreg
clock. Given the sysreg clock is provided by this CMU, this CMU's usage
count is therefore bumped and RPM can not be entered as this CMU never
becomes idle.
Switch to using device_node_to_regmap() which doesn't handle resources
(the clock), leaving the CMU's usage count unaffected.
Note1: sysreg clock handling is completely removed with this commit
because sysreg register access is only required during suspend/resume.
In the runtime suspend case, we would have to enable the clock to read
the registers, but we can not do that as that would cause a resume of
this driver which is not allowed. This is not a problem because we
would only need to handle the clock manually if automatic clock gating
wasn't enabled in the first. This code is only relevant if automatic
clock gating is enabled, though.
Fixes: 298fac4f4b96 ("clk: samsung: Implement automatic clock gating mode for CMUs")
Signed-off-by: André Draszik <andre.draszik@...aro.org>
---
drivers/clk/samsung/clk.c | 92 +++++++++++++++++++++++++++++++++++------------
drivers/clk/samsung/clk.h | 2 ++
2 files changed, 71 insertions(+), 23 deletions(-)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 9f68f079fd552f8dfb6898dbfb47dec0e84c626c..6515df81fcbc79b90f5262843e67575f6a4e0dda 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -9,11 +9,13 @@
*/
#include <linux/slab.h>
+#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
+#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/syscore_ops.h>
@@ -489,6 +491,50 @@ void __init samsung_cmu_register_clocks(struct samsung_clk_provider *ctx,
samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks);
}
+static int samsung_get_sysreg_regmap(struct device_node *np,
+ struct samsung_clk_provider *ctx)
+{
+ struct device_node *sysreg_np;
+ struct clk *sysreg_clk;
+ struct regmap *regmap;
+ int ret;
+
+ sysreg_np = of_parse_phandle(np, "samsung,sysreg", 0);
+ if (!sysreg_np)
+ return -ENODEV;
+
+ sysreg_clk = of_clk_get(sysreg_np, 0);
+ if (IS_ERR(sysreg_clk)) {
+ ret = PTR_ERR(sysreg_clk);
+ /* clock is optional */
+ if (ret != -ENOENT) {
+ pr_warn("%pOF: Unable to get sysreg clock: %d\n", np,
+ ret);
+ goto put_sysreg_np;
+ }
+ sysreg_clk = NULL;
+ }
+
+ regmap = device_node_to_regmap(sysreg_np);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ pr_warn("%pOF: Unable to get CMU sysreg: %d\n", np, ret);
+ goto put_clk;
+ }
+
+ ctx->sysreg_clk = sysreg_clk;
+ ctx->sysreg = regmap;
+
+ of_node_put(sysreg_np);
+ return 0;
+
+put_clk:
+ clk_put(sysreg_clk);
+put_sysreg_np:
+ of_node_put(sysreg_np);
+ return ret;
+}
+
/* Each bit enable/disables DRCG of a bus component */
#define DRCG_EN_MSK GENMASK(31, 0)
#define MEMCLK_EN BIT(0)
@@ -499,32 +545,32 @@ void samsung_en_dyn_root_clk_gating(struct device_node *np,
const struct samsung_cmu_info *cmu,
bool cmu_has_pm)
{
+ int ret;
+
if (!ctx->auto_clock_gate)
return;
- ctx->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg");
- if (IS_ERR(ctx->sysreg)) {
- pr_warn("%pOF: Unable to get CMU sysreg\n", np);
- ctx->sysreg = NULL;
- } else {
- /* Enable DRCG for all bus components */
- regmap_write(ctx->sysreg, ctx->drcg_offset, DRCG_EN_MSK);
- /* Enable memclk gate (not present on all sysreg) */
- if (ctx->memclk_offset)
- regmap_write_bits(ctx->sysreg, ctx->memclk_offset,
- MEMCLK_EN, 0x0);
-
- if (!cmu_has_pm)
- /*
- * When a CMU has PM support, clocks are saved/restored
- * via its PM handlers, so only register them with the
- * syscore suspend / resume paths if PM is not in use.
- */
- samsung_clk_extended_sleep_init(NULL, ctx->sysreg,
- cmu->sysreg_clk_regs,
- cmu->nr_sysreg_clk_regs,
- NULL, 0);
- }
+ ret = samsung_get_sysreg_regmap(np, ctx);
+ if (ret)
+ return;
+
+ /* Enable DRCG for all bus components */
+ regmap_write(ctx->sysreg, ctx->drcg_offset, DRCG_EN_MSK);
+ /* Enable memclk gate (not present on all sysreg) */
+ if (ctx->memclk_offset)
+ regmap_write_bits(ctx->sysreg, ctx->memclk_offset,
+ MEMCLK_EN, 0x0);
+
+ if (!cmu_has_pm)
+ /*
+ * When a CMU has PM support, clocks are saved/restored via its
+ * PM handlers, so only register them with the syscore
+ * suspend / resume paths if PM is not in use.
+ */
+ samsung_clk_extended_sleep_init(NULL, ctx->sysreg,
+ cmu->sysreg_clk_regs,
+ cmu->nr_sysreg_clk_regs,
+ NULL, 0);
}
/*
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index b1192ca03db5035cc485771ff5597cf132234a2a..deb426fbb0942f21b63c583f0ad55738239b04e4 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -21,6 +21,7 @@
* @reg_base: virtual address for the register base
* @dev: clock provider device needed for runtime PM
* @sysreg: syscon regmap for clock-provider sysreg controller
+ * @sysreg_clk: clock for sysreg access, if required
* @lock: maintains exclusion between callbacks for a given clock-provider
* @auto_clock_gate: enable auto clk mode for all clocks in clock-provider
* @gate_dbg_offset: gate debug reg offset. Used for all gates in auto clk mode
@@ -33,6 +34,7 @@ struct samsung_clk_provider {
void __iomem *reg_base;
struct device *dev;
struct regmap *sysreg;
+ struct clk *sysreg_clk;
spinlock_t lock;
bool auto_clock_gate;
u32 gate_dbg_offset;
--
2.52.0.457.g6b5491de43-goog
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