linux-kernel - [PATCH 3/3] drm/nouveau: Increase GPFIFO ring buffer size on Maxwell+

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Message-Id: <20260109-nouveau-gpfifo-increase-v1-3-ed0be9822878@mary.zone>
Date: Fri, 09 Jan 2026 18:30:12 +0100
From: Mary Guillemard <mary@...y.zone>
To: Lyude Paul <lyude@...hat.com>, Danilo Krummrich <dakr@...nel.org>, 
 Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, 
 Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, 
 David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: dri-devel@...ts.freedesktop.org, nouveau@...ts.freedesktop.org, 
 linux-kernel@...r.kernel.org, Mary Guillemard <mary@...y.zone>
Subject: [PATCH 3/3] drm/nouveau: Increase GPFIFO ring buffer size on
 Maxwell+

Since Tesla days, the limit has been increased considerably.

>From the various testing I did, since at least Maxwell, it is safe
to use up to at least 32768 entries and this should be matching
NVIDIA proprietary driver behavior.

This patch increase the ring buffer to 32768 entries on Maxwell and
later allowing up to 16382 entries to be used by the userspace.

Signed-off-by: Mary Guillemard <mary@...y.zone>
---
 drivers/gpu/drm/nouveau/nouveau_abi16.c | 22 ++++++++++++++++++----
 drivers/gpu/drm/nouveau/nouveau_chan.h  |  6 +++++-
 2 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index a5445e97179f..d4a25a442568 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -233,10 +233,24 @@ static inline int
 getparam_dma_ib_max(struct nvif_device *device)
 {
 	const struct nvif_mclass hosts[] = {
-		{ NV03_CHANNEL_DMA, 0 },
-		{ NV10_CHANNEL_DMA, 0 },
-		{ NV17_CHANNEL_DMA, 0 },
-		{ NV40_CHANNEL_DMA, 0 },
+		{ BLACKWELL_CHANNEL_GPFIFO_B, 0 },
+		{ BLACKWELL_CHANNEL_GPFIFO_A, 0 },
+		{    HOPPER_CHANNEL_GPFIFO_A, 0 },
+		{    AMPERE_CHANNEL_GPFIFO_B, 0 },
+		{    AMPERE_CHANNEL_GPFIFO_A, 0 },
+		{    TURING_CHANNEL_GPFIFO_A, 0 },
+		{     VOLTA_CHANNEL_GPFIFO_A, 0 },
+		{    PASCAL_CHANNEL_GPFIFO_A, 0 },
+		{   MAXWELL_CHANNEL_GPFIFO_A, 0 },
+		{    KEPLER_CHANNEL_GPFIFO_B, 0 },
+		{    KEPLER_CHANNEL_GPFIFO_A, 0 },
+		{     FERMI_CHANNEL_GPFIFO  , 0 },
+		{       G82_CHANNEL_GPFIFO  , 0 },
+		{      NV50_CHANNEL_GPFIFO  , 0 },
+		{      NV40_CHANNEL_DMA     , 0 },
+		{      NV17_CHANNEL_DMA     , 0 },
+		{      NV10_CHANNEL_DMA     , 0 },
+		{      NV03_CHANNEL_DMA     , 0 },
 		{}
 	};
 	int cid;
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h
index 294d061497c0..708ded06a859 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.h
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.h
@@ -67,13 +67,17 @@ int  nouveau_channel_idle(struct nouveau_channel *);
 void nouveau_channel_kill(struct nouveau_channel *);
 
 /* Maximum GPFIFO entries per channel. */
-#define NV50_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT (0x02000 / 8)
+#define NV50_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT		(0x02000 / 8)
+#define MAXWELL_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT	(0x40000 / 8)
 
 static inline u32 nouveau_channel_get_gpfifo_entries_count(u32 oclass)
 {
 	if (oclass < NV50_CHANNEL_GPFIFO)
 		return 0;
 
+	if (oclass >= MAXWELL_CHANNEL_GPFIFO_A)
+		return MAXWELL_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT;
+
 	return NV50_CHANNEL_GPFIFO_ENTRIES_MAX_COUNT;
 }
 

-- 
2.52.0