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Message-Id: <20260109032810.204-1-hehuan1@eswincomputing.com>
Date: Fri, 9 Jan 2026 11:28:10 +0800
From: hehuan1@...incomputing.com
To: adrian.hunter@...el.com,
ulf.hansson@...aro.org,
linux-mmc@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: ningyu@...incomputing.com,
linmin@...incomputing.com,
pinkesh.vaghela@...fochips.com,
xuxiang@...incomputing.com,
hehuan1@...incomputing.com
Subject: [PATCH v1] mmc: sdhci-of-dwcmshc: fix init for AXI clock and DMA 128MB boundary
From: Huan He <hehuan1@...incomputing.com>
1.Accessing the High-Speed registers requires the AXI clock to be enabled.
2.This DWC MSHC has a 128MB limitation where the data buffer size and
start address must not exceed the 128MB boundary. Registering the
missing 'adma_write_desc' callback function.
Signed-off-by: Huan He <hehuan1@...incomputing.com>
---
drivers/mmc/host/sdhci-of-dwcmshc.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 51949cde0958..147f8046707f 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -1588,6 +1588,7 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
{
u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
unsigned int val, hsp_int_status, hsp_pwr_ctrl;
+ static const char * const clk_ids[] = {"axi"};
struct of_phandle_args args;
struct eic7700_priv *priv;
struct regmap *hsp_regmap;
@@ -1605,6 +1606,11 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm
return ret;
}
+ ret = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,
+ ARRAY_SIZE(clk_ids), clk_ids);
+ if (ret)
+ return ret;
+
ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args);
if (ret) {
dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret);
@@ -1726,6 +1732,7 @@ static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = {
.set_uhs_signaling = sdhci_eic7700_set_uhs_wrapper,
.set_power = sdhci_set_power_and_bus_voltage,
.irq = dwcmshc_cqe_irq_handler,
+ .adma_write_desc = dwcmshc_adma_write_desc,
.platform_execute_tuning = sdhci_eic7700_executing_tuning,
};
--
2.25.1
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