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Message-ID: <2fc40495-2b72-43a9-ad98-7d58961877fe@lunn.ch>
Date: Fri, 9 Jan 2026 19:38:42 +0100
From: Andrew Lunn <andrew@...n.ch>
To: "illusion.wang" <illusion.wang@...ula-matrix.com>
Cc: dimon.zhao@...ula-matrix.com, alvin.wang@...ula-matrix.com,
sam.chen@...ula-matrix.com, netdev@...r.kernel.org,
andrew+netdev@...n.ch, corbet@....net, kuba@...nel.org,
linux-doc@...r.kernel.org, lorenzo@...nel.org, pabeni@...hat.com,
horms@...nel.org, vadim.fedorenko@...ux.dev,
lukas.bulwahn@...hat.com, edumazet@...gle.com,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 net-next 08/15] net/nebula-matrix: add vsi, queue,
adminq resource definitions and implementation
> +static s32 nbl_res_aq_get_module_bitrate(struct nbl_resource_mgt *res_mgt,
> + u8 eth_id)
> +{
> + struct device *dev = NBL_COMMON_TO_DEV(res_mgt->common);
> + struct nbl_eth_info *eth_info = NBL_RES_MGT_TO_ETH_INFO(res_mgt);
> + u8 data[SFF_8472_SIGNALING_RATE_MAX + 1];
> + u32 result;
> + u8 br_nom;
> + u8 br_max;
> + u8 identifier;
> + u8 encoding = 0;
> + int port_max_rate;
> + int ret;
> +
> + if (res_mgt->resource_info->board_info.eth_speed ==
> + NBL_FW_PORT_SPEED_100G) {
> + ret = nbl_res_aq_turn_module_eeprom_page(res_mgt, eth_id, 0);
> + if (ret) {
> + dev_err(dev,
> + "eth %d get_module_eeprom_info failed %d\n",
> + eth_info->logic_eth_id[eth_id], ret);
> + return NBL_PORT_MAX_RATE_UNKNOWN;
> + }
> + }
> +
> + ret = nbl_res_aq_get_module_eeprom(res_mgt, eth_id, I2C_DEV_ADDR_A0, 0,
> + 0, 0,
> + SFF_8472_SIGNALING_RATE_MAX + 1,
> + data);
> + if (ret) {
> + dev_err(dev, "eth %d get_module_eeprom_info failed %d\n",
> + eth_info->logic_eth_id[eth_id], ret);
> + return NBL_PORT_MAX_RATE_UNKNOWN;
> + }
> +
> + if (res_mgt->resource_info->board_info.eth_speed ==
> + NBL_FW_PORT_SPEED_100G) {
> + ret = nbl_res_aq_get_module_eeprom(res_mgt, eth_id,
> + I2C_DEV_ADDR_A0, 0, 0,
> + SFF_8636_VENDOR_ENCODING, 1,
> + &encoding);
> + if (ret) {
> + dev_err(dev,
> + "eth %d get_module_eeprom_info failed %d\n",
> + eth_info->logic_eth_id[eth_id], ret);
> + return NBL_PORT_MAX_RATE_UNKNOWN;
> + }
> + }
> +
> + br_nom = data[SFF_8472_SIGNALING_RATE];
> + br_max = data[SFF_8472_SIGNALING_RATE_MAX];
> + identifier = data[SFF_8472_IDENTIFIER];
> +
> + /* sff-8472 section 5.6 */
> + if (br_nom == 255)
> + result = (u32)br_max * 250;
> + else if (br_nom == 0)
> + result = 0;
> + else
> + result = (u32)br_nom * 100;
> +
> + switch (result / 1000) {
> + case 25:
> + port_max_rate = NBL_PORT_MAX_RATE_25G;
> + break;
> + case 10:
> + port_max_rate = NBL_PORT_MAX_RATE_10G;
> + break;
> + case 1:
> + port_max_rate = NBL_PORT_MAX_RATE_1G;
> + break;
> + default:
> + port_max_rate = NBL_PORT_MAX_RATE_UNKNOWN;
> + break;
> + }
> +
> + if (identifier == SFF_IDENTIFIER_QSFP28)
> + port_max_rate = NBL_PORT_MAX_RATE_100G;
> +
> + if (identifier == SFF_IDENTIFIER_PAM4 ||
> + encoding == SFF_8636_ENCODING_PAM4)
> + port_max_rate = NBL_PORT_MAX_RATE_100G_PAM4;
> +
> + return port_max_rate;
> +}
Please could you pull everything dealing with the SFP into a patch of
its own. We will want to review this code and think about if you
should be using phylink.
Do you also have a PCS which the driver is configuring? If so, please
make that a separate patch as well.
Andrew
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