[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAMuHMdW-CSVVDHXEXA5GwjERKaUHO4xxd9HCX0nez0vtCT18PA@mail.gmail.com>
Date: Fri, 9 Jan 2026 19:35:43 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
Cc: tomm.merciai@...il.com, linux-renesas-soc@...r.kernel.org,
biju.das.jz@...renesas.com, Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>, Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Magnus Damm <magnus.damm@...il.com>, dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: Re: [PATCH 03/22] clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks
On Wed, 26 Nov 2025 at 15:08, Tommaso Merciai
<tommaso.merciai.xr@...renesas.com> wrote:
> Add support for the PLLDSI{0,1} clocks in the r9a09g047 CPG driver.
>
> Introduce CLK_PLLDSI{0,1} also, introduce the
> rzg3e_cpg_pll_dsi{0,1}_limits structures to describe the frequency
> constraints specific to the RZ/G3E SoC.
>
> On Renesas RZ/G3E:
>
> - PLLDSI0 maximum output frequency: 1218 MHz
> - PLLDSI1 maximum output frequency: 609 MHz
>
> These limits are enforced through the newly added
> RZG3E_CPG_PLL_DSI{0,1}_LIMITS().
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
> --- a/include/linux/clk/renesas.h
> +++ b/include/linux/clk/renesas.h
> @@ -153,6 +153,26 @@ struct rzv2h_pll_div_pars {
> .k = { .min = -32768, .max = 32767 }, \
> } \
>
> +#define RZG3E_CPG_PLL_DSI0_LIMITS(name) \
> + static const struct rzv2h_pll_limits (name) = { \
> + .fout = { .min = 25 * MEGA, .max = 1218 * MEGA }, \
> + .fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \
> + .m = { .min = 64, .max = 533 }, \
> + .p = { .min = 1, .max = 4 }, \
> + .s = { .min = 0, .max = 6 }, \
> + .k = { .min = -32768, .max = 32767 }, \
> + } \
> +
> +#define RZG3E_CPG_PLL_DSI1_LIMITS(name) \
> + static const struct rzv2h_pll_limits (name) = { \
> + .fout = { .min = 25 * MEGA, .max = 609 * MEGA }, \
> + .fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \
> + .m = { .min = 64, .max = 533 }, \
> + .p = { .min = 1, .max = 4 }, \
> + .s = { .min = 0, .max = 6 }, \
> + .k = { .min = -32768, .max = 32767 }, \
> + } \
> +
> #ifdef CONFIG_CLK_RZV2H
> bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
> struct rzv2h_pll_pars *pars, u64 freq_millihz);
So these definitions are shared with the DRM driver, and thus are a
hard dependency from DRM to clock driver.
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Powered by blists - more mailing lists