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Message-ID: <20260109080054.228671-3-andyshrk@163.com>
Date: Fri, 9 Jan 2026 16:00:45 +0800
From: Andy Yan <andyshrk@....com>
To: heiko@...ech.de,
dmitry.baryshkov@....qualcomm.com
Cc: krzk+dt@...nel.org,
conor+dt@...nel.org,
cristian.ciocaltea@...labora.com,
Laurent.pinchart@...asonboard.com,
mripard@...nel.org,
hjc@...k-chips.com,
robh@...nel.org,
sebastian.reichel@...labora.com,
tzimmermann@...e.de,
devicetree@...r.kernel.org,
dri-devel@...ts.freedesktop.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-rockchip@...ts.infradead.org,
Andy Yan <andy.yan@...k-chips.com>
Subject: [PATCH 2/5] drm/bridge: synopsys: dw-dp: Set pixel mode by platform data
From: Andy Yan <andy.yan@...k-chips.com>
The DW DisplayPort hardware block can be configured to work in single,
dual,quad pixel mode on differnt platforms, so make the pixel mode set
by plat_data to support the upcoming rk3576 variant.
Signed-off-by: Andy Yan <andy.yan@...k-chips.com>
---
drivers/gpu/drm/bridge/synopsys/dw-dp.c | 8 +-------
drivers/gpu/drm/rockchip/dw_dp-rockchip.c | 19 +++++++++++++++----
include/drm/bridge/dw_dp.h | 7 +++++++
3 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
index 82aaf74e1bc0..eccf6299bdb7 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
@@ -352,12 +352,6 @@ enum {
DW_DP_YCBCR420_16BIT,
};
-enum {
- DW_DP_MP_SINGLE_PIXEL,
- DW_DP_MP_DUAL_PIXEL,
- DW_DP_MP_QUAD_PIXEL,
-};
-
enum {
DW_DP_SDP_VERTICAL_INTERVAL = BIT(0),
DW_DP_SDP_HORIZONTAL_INTERVAL = BIT(1),
@@ -1984,7 +1978,7 @@ struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
return ERR_CAST(dp);
dp->dev = dev;
- dp->pixel_mode = DW_DP_MP_QUAD_PIXEL;
+ dp->pixel_mode = plat_data->pixel_mode;
dp->plat_data.max_link_rate = plat_data->max_link_rate;
bridge = &dp->bridge;
diff --git a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
index 25ab4e46301e..89d614d53596 100644
--- a/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_dp-rockchip.c
@@ -75,7 +75,7 @@ static const struct drm_encoder_helper_funcs dw_dp_encoder_helper_funcs = {
static int dw_dp_rockchip_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
- struct dw_dp_plat_data plat_data;
+ const struct dw_dp_plat_data *plat_data;
struct drm_device *drm_dev = data;
struct rockchip_dw_dp *dp;
struct drm_encoder *encoder;
@@ -89,7 +89,10 @@ static int dw_dp_rockchip_bind(struct device *dev, struct device *master, void *
dp->dev = dev;
platform_set_drvdata(pdev, dp);
- plat_data.max_link_rate = 810000;
+ plat_data = of_device_get_match_data(dev);
+ if (!plat_data)
+ return -ENODEV;
+
encoder = &dp->encoder.encoder;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, dev->of_node);
rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder, dev->of_node, 0, 0);
@@ -99,7 +102,7 @@ static int dw_dp_rockchip_bind(struct device *dev, struct device *master, void *
return ret;
drm_encoder_helper_add(encoder, &dw_dp_encoder_helper_funcs);
- dp->base = dw_dp_bind(dev, encoder, &plat_data);
+ dp->base = dw_dp_bind(dev, encoder, plat_data);
if (IS_ERR(dp->base)) {
ret = PTR_ERR(dp->base);
return ret;
@@ -134,8 +137,16 @@ static void dw_dp_remove(struct platform_device *pdev)
component_del(dp->dev, &dw_dp_rockchip_component_ops);
}
+static const struct dw_dp_plat_data rk3588_dp_plat_data = {
+ .max_link_rate = 810000,
+ .pixel_mode = DW_DP_MP_QUAD_PIXEL,
+};
+
static const struct of_device_id dw_dp_of_match[] = {
- { .compatible = "rockchip,rk3588-dp", },
+ {
+ .compatible = "rockchip,rk3588-dp",
+ .data = &rk3588_dp_plat_data,
+ },
{}
};
MODULE_DEVICE_TABLE(of, dw_dp_of_match);
diff --git a/include/drm/bridge/dw_dp.h b/include/drm/bridge/dw_dp.h
index d05df49fd884..25363541e69d 100644
--- a/include/drm/bridge/dw_dp.h
+++ b/include/drm/bridge/dw_dp.h
@@ -11,8 +11,15 @@
struct drm_encoder;
struct dw_dp;
+enum {
+ DW_DP_MP_SINGLE_PIXEL,
+ DW_DP_MP_DUAL_PIXEL,
+ DW_DP_MP_QUAD_PIXEL,
+};
+
struct dw_dp_plat_data {
u32 max_link_rate;
+ u8 pixel_mode;
};
struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
--
2.43.0
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