linux-kernel - Re: [PATCH v5 5/5] power: sequencing: Add the Power Sequencing driver for the PCIe M.2 connectors

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Message-ID: <375ea14c-b089-4ae4-9827-5c19139f69c4@kernel.org>
Date: Fri, 9 Jan 2026 10:02:10 +0100
From: Damien Le Moal <dlemoal@...nel.org>
To: Manivannan Sadhasivam <mani@...nel.org>,
 Bartosz Golaszewski <brgl@...nel.org>
Cc: manivannan.sadhasivam@....qualcomm.com,
 Bjorn Helgaas <bhelgaas@...gle.com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Niklas Cassel <cassel@...nel.org>,
 Linus Walleij <linus.walleij@...aro.org>, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
 linux-arm-msm@...r.kernel.org, Stephan Gerhold <stephan.gerhold@...aro.org>,
 Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
 linux-pm@...r.kernel.org, linux-ide@...r.kernel.org
Subject: Re: [PATCH v5 5/5] power: sequencing: Add the Power Sequencing driver
 for the PCIe M.2 connectors

On 1/9/26 07:02, Manivannan Sadhasivam wrote:
> On Thu, Jan 08, 2026 at 01:15:12PM +0100, Bartosz Golaszewski wrote:
>> On Wed, Jan 7, 2026 at 3:11 PM Manivannan Sadhasivam via B4 Relay
>> <devnull+manivannan.sadhasivam.oss.qualcomm.com@...nel.org> wrote:
>>>
>>> From: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
>>>
>>> This driver is used to control the PCIe M.2 connectors of different
>>> Mechanical Keys attached to the host machines and supporting different
>>> interfaces like PCIe/SATA, USB/UART etc...
>>>
>>> Currently, this driver supports only the Mechanical Key M connectors with
>>> PCIe interface. The driver also only supports driving the mandatory 3.3v
>>> and optional 1.8v power supplies. The optional signals of the Key M
>>> connectors are not currently supported.
>>>
>>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
>>
>> This looks good to me, though there are some nits I may fix when applying.
>>
>> I'll pick it up for v7.0 once the bindings are reviewed.
>>
> 
> Ok. I'm expecting patch 1 to go through ATA tree, patch 2 through DT, and
> patches 3,4 through PCI tree.

Patch 1 seems to be completely unrelated to the power changes, so please send it
to the ata list separately. It is otherwise very complicated and confusing for
everyone to have patches from one series being applied through multiple trees.


-- 
Damien Le Moal
Western Digital Research