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Message-ID: <20260109090224.3105465-8-himanshu.chauhan@oss.qualcomm.com>
Date: Fri, 9 Jan 2026 14:32:21 +0530
From: Himanshu Chauhan <himanshu.chauhan@....qualcomm.com>
To: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-acpi@...r.kernel.org, linux-efi@...r.kernel.org,
acpica-devel@...ts.linux.dev, paul.walmsley@...ive.com,
palmer@...belt.com, lenb@...nel.org, james.morse@....com,
tony.luck@...el.com, ardb@...nel.org, conor@...nel.org,
cleger@...osinc.com, robert.moore@...el.com, sunilvl@....qualcomm.com,
anup.patel@....qualcomm.com
Cc: Himanshu Chauhan <himanshu.chauhan@....qualcomm.com>
Subject: [PATCH v3 07/10] riscv: Add RISC-V entries in processor type and ISA strings
Add RISCV and RISCV32/64 strings in the in processor type and ISA strings
respectively. These are defined for cper records.
Signed-off-by: Himanshu Chauhan <himanshu.chauhan@....qualcomm.com>
---
drivers/firmware/efi/cper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c
index 0232bd040f61..9d591a294327 100644
--- a/drivers/firmware/efi/cper.c
+++ b/drivers/firmware/efi/cper.c
@@ -170,6 +170,7 @@ static const char * const proc_type_strs[] = {
"IA32/X64",
"IA64",
"ARM",
+ "RISCV",
};
static const char * const proc_isa_strs[] = {
@@ -178,6 +179,8 @@ static const char * const proc_isa_strs[] = {
"X64",
"ARM A32/T32",
"ARM A64",
+ "RISCV32",
+ "RISCV64",
};
const char * const cper_proc_error_type_strs[] = {
--
2.43.0
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