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Message-ID: <b05d4feb-e3b7-43ab-b8bc-596302ec8c77@foss.st.com>
Date: Fri, 9 Jan 2026 10:09:14 +0100
From: Patrice CHOTARD <patrice.chotard@...s.st.com>
To: Alexandre TORGUE <alexandre.torgue@...s.st.com>, Rob Herring
<robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Maxime Coquelin <mcoquelin.stm32@...il.com>, "Patrick
Delaunay" <patrick.delaunay@...s.st.com>
CC: <devicetree@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 5/6] ARM: dts: stm32: Add boot phase tags for
STMicroelectronics mp15 boards
On 1/9/26 09:19, Alexandre TORGUE wrote:
> Hi Patrice
>
> On 1/8/26 18:16, Patrice Chotard wrote:
>> The bootph-all flag was introduced in dt-schema
>> (dtschema/schemas/bootph.yaml) to define node usage across
>> different boot phases.
>>
>> To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
>> present in all boot stages, so add missing bootph-all phase flag
>> to these nodes to support SD boot.
>>
>> Signed-off-by: Patrice Chotard <patrice.chotard@...s.st.com>
>> ---
>> arch/arm/boot/dts/st/stm32mp15-scmi.dtsi | 26 ++++++++++++
>> arch/arm/boot/dts/st/stm32mp151.dtsi | 29 +++++++++++++
>> arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 14 +++++++
>> arch/arm/boot/dts/st/stm32mp157a-dk1.dts | 43 +++++++++++++++++++
>> arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 43 +++++++++++++++++++
>> arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 14 +++++++
>> arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 60 +++++++++++++++++++++++++++
>> arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 25 +++++++++++
>> arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 36 ++++++++++++++++
>> 9 files changed, 290 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
>> index 98552fe45d4e..c58d81f505be 100644
>> --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
>> +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
>> @@ -13,6 +13,7 @@ optee: optee {
>> method = "smc";
>> interrupt-parent = <&intc>;
>> interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
>> + bootph-some-ram;
>> };
>> scmi: scmi {
>> @@ -20,6 +21,7 @@ scmi: scmi {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> linaro,optee-channel-id = <0>;
>> + bootph-some-ram;
>> scmi_clk: protocol@14 {
>> reg = <0x14>;
>> @@ -64,6 +66,26 @@ scmi_usb33: regulator@2 {
>> };
>> };
>> +&iwdg2 {
>> + bootph-all;
>> +};
>>
>
> node update useless as already done in stm32mp151.dtsi
you are right, i will remove this node.
>
>> +<dc {
>> + bootph-some-ram;
>> +};
>>
>
> ditto
ok>
>> +&pinctrl {
>> + bootph-all;
>> +};
>> +
>
> ditto
ok>
>> +&pinctrl_z {
>> + bootph-all;
>> +};
>>
> ditto
ok>
>> +&rcc {
>> + bootph-all;
>> +};
>>
>
> ditto
ok>
>> ®11 {
>> status = "disabled";
>> };
>> @@ -72,6 +94,10 @@ ®18 {
>> status = "disabled";
>> };
>> +&scmi {
>> + bootph-some-ram;
>> +};
>
> Already define at the top of this patch.
ok
Thanks
Patrice>
>
>
>> +
>> &usb33 {
>> status = "disabled";
>> };
>> diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
>> index b1b568dfd126..7abee7ce0580 100644
>> --- a/arch/arm/boot/dts/st/stm32mp151.dtsi
>> +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
>> @@ -33,6 +33,7 @@ arm-pmu {
>> psci {
>> compatible = "arm,psci-1.0";
>> method = "smc";
>> + bootph-some-ram;
>> };
>> intc: interrupt-controller@...21000 {
>> @@ -54,34 +55,41 @@ timer {
>> };
>> clocks {
>> + bootph-all;
>> +
>> clk_hse: clk-hse {
>> #clock-cells = <0>;
>> compatible = "fixed-clock";
>> clock-frequency = <24000000>;
>> + bootph-all;
>> };
>> clk_hsi: clk-hsi {
>> #clock-cells = <0>;
>> compatible = "fixed-clock";
>> clock-frequency = <64000000>;
>> + bootph-all;
>> };
>> clk_lse: clk-lse {
>> #clock-cells = <0>;
>> compatible = "fixed-clock";
>> clock-frequency = <32768>;
>> + bootph-all;
>> };
>> clk_lsi: clk-lsi {
>> #clock-cells = <0>;
>> compatible = "fixed-clock";
>> clock-frequency = <32000>;
>> + bootph-all;
>> };
>> clk_csi: clk-csi {
>> #clock-cells = <0>;
>> compatible = "fixed-clock";
>> clock-frequency = <4000000>;
>> + bootph-all;
>> };
>> };
>> @@ -122,6 +130,7 @@ soc {
>> #size-cells = <1>;
>> interrupt-parent = <&intc>;
>> ranges;
>> + bootph-all;
>> ipcc: mailbox@...01000 {
>> compatible = "st,stm32mp1-ipcc";
>> @@ -142,11 +151,13 @@ rcc: rcc@...00000 {
>> reg = <0x50000000 0x1000>;
>> #clock-cells = <1>;
>> #reset-cells = <1>;
>> + bootph-all;
>> };
>> pwr_regulators: pwr@...01000 {
>> compatible = "st,stm32mp1,pwr-reg";
>> reg = <0x50001000 0x10>;
>> + bootph-all;
>> reg11: reg11 {
>> regulator-name = "reg11";
>> @@ -354,6 +365,7 @@ ltdc: display-controller@...01000 {
>> clocks = <&rcc LTDC_PX>;
>> clock-names = "lcd";
>> resets = <&rcc LTDC_R>;
>> + bootph-some-ram;
>> status = "disabled";
>> };
>> @@ -364,6 +376,7 @@ iwdg2: watchdog@...02000 {
>> clock-names = "pclk", "lsi";
>> interrupts-extended = <&exti 46 IRQ_TYPE_LEVEL_HIGH>;
>> wakeup-source;
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -404,6 +417,8 @@ bsec: efuse@...05000 {
>> reg = <0x5c005000 0x400>;
>> #address-cells = <1>;
>> #size-cells = <1>;
>> + bootph-all;
>> +
>> part_number_otp: part-number-otp@4 {
>> reg = <0x4 0x1>;
>> };
>> @@ -1876,6 +1891,7 @@ pinctrl: pinctrl@...02000 {
>> ranges = <0 0x50002000 0xa400>;
>> interrupt-parent = <&exti>;
>> st,syscfg = <&exti 0x60 0xff>;
>> + bootph-all;
>> gpioa: gpio@...02000 {
>> gpio-controller;
>> @@ -1885,6 +1901,7 @@ gpioa: gpio@...02000 {
>> reg = <0x0 0x400>;
>> clocks = <&rcc GPIOA>;
>> st,bank-name = "GPIOA";
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -1896,6 +1913,7 @@ gpiob: gpio@...03000 {
>> reg = <0x1000 0x400>;
>> clocks = <&rcc GPIOB>;
>> st,bank-name = "GPIOB";
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -1907,6 +1925,7 @@ gpioc: gpio@...04000 {
>> reg = <0x2000 0x400>;
>> clocks = <&rcc GPIOC>;
>> st,bank-name = "GPIOC";
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -1918,6 +1937,7 @@ gpiod: gpio@...05000 {
>> reg = <0x3000 0x400>;
>> clocks = <&rcc GPIOD>;
>> st,bank-name = "GPIOD";
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -1929,6 +1949,7 @@ gpioe: gpio@...06000 {
>> reg = <0x4000 0x400>;
>> clocks = <&rcc GPIOE>;
>> st,bank-name = "GPIOE";
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -1940,6 +1961,7 @@ gpiof: gpio@...07000 {
>> reg = <0x5000 0x400>;
>> clocks = <&rcc GPIOF>;
>> st,bank-name = "GPIOF";
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -1951,6 +1973,7 @@ gpiog: gpio@...08000 {
>> reg = <0x6000 0x400>;
>> clocks = <&rcc GPIOG>;
>> st,bank-name = "GPIOG";
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -1962,6 +1985,7 @@ gpioh: gpio@...09000 {
>> reg = <0x7000 0x400>;
>> clocks = <&rcc GPIOH>;
>> st,bank-name = "GPIOH";
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -1973,6 +1997,7 @@ gpioi: gpio@...0a000 {
>> reg = <0x8000 0x400>;
>> clocks = <&rcc GPIOI>;
>> st,bank-name = "GPIOI";
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -1984,6 +2009,7 @@ gpioj: gpio@...0b000 {
>> reg = <0x9000 0x400>;
>> clocks = <&rcc GPIOJ>;
>> st,bank-name = "GPIOJ";
>> + bootph-all;
>> status = "disabled";
>> };
>> @@ -1995,6 +2021,7 @@ gpiok: gpio@...0c000 {
>> reg = <0xa000 0x400>;
>> clocks = <&rcc GPIOK>;
>> st,bank-name = "GPIOK";
>> + bootph-all;
>> status = "disabled";
>> };
>> };
>> @@ -2006,6 +2033,7 @@ pinctrl_z: pinctrl@...04000 {
>> ranges = <0 0x54004000 0x400>;
>> interrupt-parent = <&exti>;
>> st,syscfg = <&exti 0x60 0xff>;
>> + bootph-all;
>> gpioz: gpio@...04000 {
>> gpio-controller;
>> @@ -2016,6 +2044,7 @@ gpioz: gpio@...04000 {
>> clocks = <&rcc GPIOZ>;
>> st,bank-name = "GPIOZ";
>> st,bank-ioport = <11>;
>> + bootph-all;
>> status = "disabled";
>> };
>> };
>> diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
>> index 847b360f02fc..f721c398e576 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
>> @@ -85,3 +85,17 @@ &rng1 {
>> &rtc {
>> clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
>> };
>> +
>> +&uart4 {
>> + bootph-all;
>> +};
>> +
>> +&uart4_pins_a {
>> + bootph-all;
>> + pins1 {
>> + bootph-all;
>> + };
>> + pins2 {
>> + bootph-all;
>> + };
>> +};
>> diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
>> index 0da3667ab1e0..c4581e28504a 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
>> @@ -23,3 +23,46 @@ chosen {
>> stdout-path = "serial0:115200n8";
>> };
>> };
>> +
>> +&i2c4 {
>> + bootph-all;
>> +};
>> +
>> +&i2c4_pins_a {
>> + bootph-all;
>> + pins {
>> + bootph-all;
>> + };
>> +};
>> +
>> +&pmic {
>> + bootph-all;
>> +};
>> +
>> +&sdmmc1 {
>> + bootph-pre-ram;
>> +};
>> +
>> +&sdmmc1_b4_pins_a {
>> + bootph-pre-ram;
>> + pins1 {
>> + bootph-pre-ram;
>> + };
>> + pins2 {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> +&uart4 {
>> + bootph-all;
>> +};
>> +
>> +&uart4_pins_a {
>> + bootph-all;
>> + pins1 {
>> + bootph-all;
>> + };
>> + pins2 {
>> + bootph-all;
>> + };
>> +};
>> diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
>> index 1ec3b8f2faa9..4fc670bb4cb0 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
>> @@ -79,6 +79,17 @@ touchscreen@38 {
>> };
>> };
>> +&i2c4 {
>> + bootph-all;
>> +};
>> +
>> +&i2c4_pins_a {
>> + bootph-all;
>> + pins {
>> + bootph-all;
>> + };
>> +};
>> +
>> <dc {
>> status = "okay";
>> @@ -93,6 +104,10 @@ ltdc_ep1_out: endpoint@1 {
>> };
>> };
>> +&pmic {
>> + bootph-all;
>> +};
>> +
>> &rtc {
>> pinctrl-names = "default";
>> pinctrl-0 = <&rtc_rsvd_pins_a>;
>> @@ -103,6 +118,20 @@ rtc_lsco_pins_a: rtc-lsco-0 {
>> };
>> };
>> +&sdmmc1 {
>> + bootph-pre-ram;
>> +};
>> +
>> +&sdmmc1_b4_pins_a {
>> + bootph-pre-ram;
>> + pins1 {
>> + bootph-pre-ram;
>> + };
>> + pins2 {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> /* Wifi */
>> &sdmmc2 {
>> pinctrl-names = "default", "opendrain", "sleep";
>> @@ -127,6 +156,20 @@ brcmf: wifi@1 {
>> };
>> };
>> +&uart4 {
>> + bootph-all;
>> +};
>> +
>> +&uart4_pins_a {
>> + bootph-all;
>> + pins1 {
>> + bootph-all;
>> + };
>> + pins2 {
>> + bootph-all;
>> + };
>> +};
>> +
>> /* Bluetooth */
>> &usart2 {
>> pinctrl-names = "default", "sleep", "idle";
>> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
>> index 6f27d794d270..00d4855f9a85 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
>> @@ -90,3 +90,17 @@ &rng1 {
>> &rtc {
>> clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
>> };
>> +
>> +&uart4 {
>> + bootph-all;
>> +};
>> +
>> +&uart4_pins_a {
>> + bootph-all;
>> + pins1 {
>> + bootph-all;
>> + };
>> + pins2 {
>> + bootph-all;
>> + };
>> +};
>> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
>> index f6c478dbd041..f63a3d68d2b4 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
>> @@ -168,7 +168,9 @@ &i2c4 {
>> i2c-scl-rising-time-ns = <185>;
>> i2c-scl-falling-time-ns = <20>;
>> clock-frequency = <400000>;
>> + bootph-all;
>> status = "okay";
>> +
>> /* spare dmas for other usage */
>> /delete-property/dmas;
>> /delete-property/dma-names;
>> @@ -179,6 +181,7 @@ pmic: stpmic@33 {
>> interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> + bootph-all;
>> status = "okay";
>> regulators {
>> @@ -314,6 +317,13 @@ watchdog {
>> };
>> };
>> +&i2c4_pins_a {
>> + bootph-all;
>> + pins {
>> + bootph-all;
>> + };
>> +};
>> +
>> &ipcc {
>> status = "okay";
>> };
>> @@ -365,9 +375,30 @@ &sdmmc1 {
>> sd-uhs-sdr25;
>> sd-uhs-sdr50;
>> sd-uhs-ddr50;
>> + bootph-pre-ram;
>> status = "okay";
>> };
>> +&sdmmc1_b4_pins_a {
>> + bootph-pre-ram;
>> + pins1 {
>> + bootph-pre-ram;
>> + };
>> + pins2 {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> +&sdmmc1_dir_pins_a {
>> + bootph-pre-ram;
>> + pins1 {
>> + bootph-pre-ram;
>> + };
>> + pins2 {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> &sdmmc2 {
>> pinctrl-names = "default", "opendrain", "sleep";
>> pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
>> @@ -381,9 +412,27 @@ &sdmmc2 {
>> vmmc-supply = <&v3v3>;
>> vqmmc-supply = <&vdd>;
>> mmc-ddr-3_3v;
>> + bootph-pre-ram;
>> status = "okay";
>> };
>> +&sdmmc2_b4_pins_a {
>> + bootph-pre-ram;
>> + pins1 {
>> + bootph-pre-ram;
>> + };
>> + pins2 {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> +&sdmmc2_d47_pins_a {
>> + bootph-pre-ram;
>> + pins {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> &timers6 {
>> status = "okay";
>> /* spare dmas for other usage */
>> @@ -399,11 +448,22 @@ &uart4 {
>> pinctrl-0 = <&uart4_pins_a>;
>> pinctrl-1 = <&uart4_sleep_pins_a>;
>> pinctrl-2 = <&uart4_idle_pins_a>;
>> + bootph-all;
>> /delete-property/dmas;
>> /delete-property/dma-names;
>> status = "okay";
>> };
>> +&uart4_pins_a {
>> + bootph-all;
>> + pins1 {
>> + bootph-all;
>> + };
>> + pins2 {
>> + bootph-all;
>> + };
>> +};
>> +
>> &usbotg_hs {
>> vbus-supply = <&vbus_otg>;
>> };
>> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
>> index 6ae391bffee5..bcf80f76d6bc 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
>> @@ -77,6 +77,31 @@ &optee {
>> interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
>> };
>> +&qspi {
>> + bootph-pre-ram;
>> +};
>> +
>> +&qspi_clk_pins_a {
>> + bootph-pre-ram;
>> + pins {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> +&qspi_bk1_pins_a {
>> + bootph-pre-ram;
>> + pins {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> +&qspi_bk2_pins_a {
>> + bootph-pre-ram;
>> + pins {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> &rcc {
>> compatible = "st,stm32mp1-rcc-secure", "syscon";
>> clock-names = "hse", "hsi", "csi", "lse", "lsi";
>> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
>> index 8f99c30f1af1..879436cbb72d 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
>> @@ -262,6 +262,7 @@ &qspi_bk2_sleep_pins_a
>> reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + bootph-pre-ram;
>> status = "okay";
>> flash0: flash@0 {
>> @@ -283,6 +284,41 @@ flash1: flash@1 {
>> };
>> };
>> +&qspi_clk_pins_a {
>> + bootph-pre-ram;
>> + pins {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> +&qspi_bk1_pins_a {
>> + bootph-pre-ram;
>> + pins {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> +&qspi_cs1_pins_a {
>> + bootph-pre-ram;
>> + pins {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> +&qspi_bk2_pins_a {
>> + bootph-pre-ram;
>> + pins {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> +&qspi_cs2_pins_a {
>> + bootph-pre-ram;
>> + pins {
>> + bootph-pre-ram;
>> + };
>> +};
>> +
>> &sdmmc3 {
>> pinctrl-names = "default", "opendrain", "sleep";
>> pinctrl-0 = <&sdmmc3_b4_pins_a>;
>>
>
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