| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20260109-debug_bus-v1-6-8f2142b5a738@foss.st.com>
Date: Fri, 9 Jan 2026 11:55:06 +0100
From: Gatien Chevallier <gatien.chevallier@...s.st.com>
To: Suzuki K Poulose <suzuki.poulose@....com>,
Mike Leach
<mike.leach@...aro.org>,
James Clark <james.clark@...aro.org>, Rob Herring
<robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Leo Yan
<leo.yan@...ux.dev>,
Clément Le Goffic
<legoffic.clement@...il.com>,
Linus Walleij <linusw@...nel.org>,
"Maxime
Coquelin" <mcoquelin.stm32@...il.com>,
Alexandre Torgue
<alexandre.torgue@...s.st.com>
CC: <coresight@...ts.linaro.org>, <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-gpio@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
Gatien Chevallier <gatien.chevallier@...s.st.com>,
Antonio Borneo
<antonio.borneo@...s.st.com>
Subject: [PATCH 06/11] arm: dts: stm32: introduce the debug bus for
stm32mp1x platforms
Some peripherals cannot be probed if a debug configuration is not set
in the BSEC.
Introduce a debug bus that will check the debug subsystem accessibility
before probing these peripheral drivers.
Add Coresight peripheral nodes under this bus and add the appropriate
access-controllers property to the HDP node.
Signed-off-by: Antonio Borneo <antonio.borneo@...s.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@...s.st.com>
---
arch/arm/boot/dts/st/stm32mp131.dtsi | 119 ++++++++++++++++++++++++
arch/arm/boot/dts/st/stm32mp151.dtsi | 173 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/st/stm32mp153.dtsi | 68 ++++++++++++++
3 files changed, 360 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index b9657ff91c23..d394061b85ac 100644
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@...s.st.com> for STMicroelectronics.
*/
+#include <dt-bindings/arm/coresight-cti-dt.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp13-clks.h>
#include <dt-bindings/reset/stm32mp13-resets.h>
@@ -964,9 +965,127 @@ hdp: pinctrl@...2a000 {
compatible = "st,stm32mp131-hdp";
reg = <0x5002a000 0x400>;
clocks = <&rcc HDP>;
+ access-controllers = <&dbg_bus 1>;
status = "disabled";
};
+ dbg_bus: bus@...80000 {
+ compatible = "st,stm32mp131-dbg-bus";
+ reg = <0x50080000 0x3f80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&rcc CK_DBG>;
+ #access-controller-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ cs_etf: etf@...92000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x50092000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ etf_in_port: endpoint {
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf_out_port: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ };
+ };
+
+ cs_tpiu: tpiu@...93000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x50093000 0x1000>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
+ cs_cti_trace: cti@...94000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x50094000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+ };
+
+ cs_cti_cpu0: cti@...d8000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x500d8000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ trig-conns@0 {
+ reg = <0>;
+ arm,trig-in-sigs = <0 4 5>;
+ arm,trig-in-types = <PE_DBGTRIGGER
+ GEN_IO
+ GEN_IO>;
+ arm,trig-out-sigs = <0 7>;
+ arm,trig-out-types = <PE_EDBGREQ
+ PE_DBGRESTART>;
+ cpu = <&cpu0>;
+ };
+
+ trig-conns@2 {
+ reg = <2>;
+ arm,trig-in-sigs = <2 3 6>;
+ arm,trig-in-types = <ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT>;
+ arm,trig-out-sigs = <1 2 3 4>;
+ arm,trig-out-types = <ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN>;
+ arm,cs-dev-assoc = <&cs_etm0>;
+ };
+ };
+
+ cs_etm0: etm@...dc000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dc000 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ etm0_out_port: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+ };
+ };
+ };
+
mdma: dma-controller@...00000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
index b1b568dfd126..a6371d626a2e 100644
--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@...com> for STMicroelectronics.
*/
+#include <dt-bindings/arm/coresight-cti-dt.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
@@ -274,9 +275,181 @@ hdp: pinctrl@...2a000 {
compatible = "st,stm32mp151-hdp";
reg = <0x5002a000 0x400>;
clocks = <&rcc HDP>;
+ access-controllers = <&dbg_bus 1>;
status = "disabled";
};
+ dbg_bus: bus@...80000 {
+ compatible = "st,stm32mp151-dbg-bus";
+ reg = <0x50080000 0x3f80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&rcc CK_DBG>;
+ #access-controller-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ cs_funnel: funnel@...91000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x50091000 0x1000>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_in_port0: endpoint {
+ remote-endpoint = <&stm_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_in_port1: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_out_port: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+ };
+ };
+
+ cs_etf: etf@...92000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x50092000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ etf_in_port: endpoint {
+ remote-endpoint = <&funnel_out_port>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf_out_port: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ };
+ };
+
+ cs_tpiu: tpiu@...93000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x50093000 0x1000>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
+ cs_cti_trace: cti@...94000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x50094000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+ };
+
+ cs_stm: stm@...a0000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x500a0000 0x00001000>,
+ <0x90000000 0x01000000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ stm_out_port: endpoint {
+ remote-endpoint = <&funnel_in_port0>;
+ };
+ };
+ };
+ };
+
+ cs_cti_cpu0: cti@...d8000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x500d8000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ trig-conns@0 {
+ reg = <0>;
+ arm,trig-in-sigs = <0 4 5>;
+ arm,trig-in-types = <PE_DBGTRIGGER
+ GEN_IO
+ GEN_IO>;
+ arm,trig-out-sigs = <0 7>;
+ arm,trig-out-types = <PE_EDBGREQ
+ PE_DBGRESTART>;
+ cpu = <&cpu0>;
+ };
+
+ trig-conns@2 {
+ reg = <2>;
+ arm,trig-in-sigs = <2 3 6>;
+ arm,trig-in-types = <ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT>;
+ arm,trig-out-sigs = <1 2 3 4>;
+ arm,trig-out-types = <ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN>;
+ arm,cs-dev-assoc = <&cs_etm0>;
+ };
+ };
+
+ cs_etm0: etm@...dc000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dc000 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&funnel_in_port1>;
+ };
+ };
+ };
+ };
+ };
+
mdma1: dma-controller@...00000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi
index 92794b942ab2..17d52d93695e 100644
--- a/arch/arm/boot/dts/st/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp153.dtsi
@@ -30,6 +30,74 @@ timer {
};
};
+&cs_funnel {
+ in-ports {
+ port@2 {
+ reg = <2>;
+ funnel_in_port2: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+};
+
+&dbg_bus {
+ cs_cti_cpu1: cti@...d9000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x500d9000 0x1000>;
+ clocks = <&rcc CK_DBG>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ trig-conns@0 {
+ reg = <0>;
+ arm,trig-in-sigs = <0 4 5>;
+ arm,trig-in-types = <PE_DBGTRIGGER
+ GEN_IO
+ GEN_IO>;
+ arm,trig-out-sigs = <0 7>;
+ arm,trig-out-types = <PE_EDBGREQ
+ PE_DBGRESTART>;
+ cpu = <&cpu1>;
+ };
+
+ trig-conns@2 {
+ reg = <2>;
+ arm,trig-in-sigs = <2 3 6>;
+ arm,trig-in-types = <ETM_EXTOUT
+ ETM_EXTOUT
+ ETM_EXTOUT>;
+ arm,trig-out-sigs = <1 2 3 4>;
+ arm,trig-out-types = <ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN
+ ETM_EXTIN>;
+ arm,cs-dev-assoc = <&cs_etm1>;
+ };
+ };
+
+ cs_etm1: etm@...dd000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x500dd000 0x1000>;
+ cpu = <&cpu1>;
+ clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+ clock-names = "apb_pclk", "atclk";
+ access-controllers = <&dbg_bus 0>;
+ status = "disabled";
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&funnel_in_port2>;
+ };
+ };
+ };
+ };
+};
+
&etzpc {
m_can1: can@...0e000 {
compatible = "bosch,m_can";
--
2.43.0
Powered by blists - more mailing lists