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Message-ID: <CAAhV-H7a5tmY2D7s-dpY8NkFCRx9rTX2mgCjgF0D_EdJHY5x6w@mail.gmail.com>
Date: Sat, 10 Jan 2026 11:48:46 +0800
From: Huacai Chen <chenhuacai@...il.com>
To: Thomas Gleixner <tglx@...nel.org>
Cc: Huacai Chen <chenhuacai@...ngson.cn>, loongarch@...ts.linux.dev, 
	linux-kernel@...r.kernel.org, Xuefeng Li <lixuefeng@...ngson.cn>, 
	Jiaxun Yang <jiaxun.yang@...goat.com>
Subject: Re: [PATCH 1/7] irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT

On Fri, Jan 9, 2026 at 8:09 PM Thomas Gleixner <tglx@...nel.org> wrote:
>
> On Tue, Dec 23 2025 at 16:04, Huacai Chen wrote:
>
> > csr_read64() is only available on 64BIT LoongArch platform, so use
> > recently added adaptive csr_read() instead, so as to make the driver
> > work on both 32BIT and 64BIT platform.
> >
> > BTW, make avecintc_enable() be a no-op since it is only needed by 64BIT
> > platform.
> >
> > Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com>
> > Signed-off-by: Huacai Chen <chenhuacai@...ngson.cn>
>
> I assume Jiaxun is the author, which means that this lacks a
>
>   From: Jiaxun
>
> line in the mail body before the change log starts. Please try again.
We are co-developer, so I think

Co-developed-by: Jiaxun Yang <jiaxun.yang@...goat.com>

is appropriate.

>
> >  static inline void avecintc_enable(void)
> >  {
> > +#ifdef CONFIG_MACH_LOONGSON64
> >       u64 value;
> >
> >       value = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
> >       value |= IOCSR_MISC_FUNC_AVEC_EN;
> >       iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC);
> > +#endif
>
> Can't this be:
>
>       if (IS_ENABLED(CONFIG_MACH_LOONGSON64))
>
> which is preferred over ifdeffery?
OK, I will do it in the next version.

Huacai

>
> Thanks,
>
>         tglx
>

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