linux-kernel - [PATCH v10 loongarch-next 0/3] LoongArch: Add 128-bit atomic cmpxchg support

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Message-ID: <20260110131124.99866-1-dongtai.guo@linux.dev>
Date: Sat, 10 Jan 2026 21:11:21 +0800
From: George Guo <dongtai.guo@...ux.dev>
To: chenhuacai@...nel.org
Cc: dongtai.guo@...ux.dev,
	guodongtai@...inos.cn,
	hengqi.chen@...il.com,
	kernel@...0n.name,
	lianyangyang@...inos.cn,
	linux-kernel@...r.kernel.org,
	loongarch@...ts.linux.dev,
	r@....cc,
	xry111@...111.site
Subject: [PATCH v10 loongarch-next 0/3] LoongArch: Add 128-bit atomic cmpxchg support

This patch series adds 128-bit atomic compare-and-exchange support for
LoongArch architecture, which fixes BPF scheduler test failures caused
by missing 128-bit atomics support.

---
Changes in v10:
- move "scq" to be placed after "lam" 
- squash last patch 
- move patch: "LoongArch: Replace seq_printf with seq_puts for simple strings" to the end
- Link to v9: https://lore.kernel.org/all/20260105105514.76021-1-dongtai.guo@linux.dev/

---
Changes in v9:
- Add patch: "LoongArch: Replace seq_printf with seq_puts for simple strings"
- #define system_has_cmpxchg128() (cpu_has_scq) 
- Delete __cmpxchg128_locked
- #define HWCAP_LOONGARCH_CPU_SCQ (1 << 15) in hwcap.h
- Link to v8: https://lore.kernel.org/all/20251231034523.47014-1-dongtai.guo@linux.dev/

---
Changes in v8:
- Merge patch 2 and patch 3 into one patch
- Put HAVE_CMPXCHG_DOUBLE in order
- Link to v7: https://lore.kernel.org/all/20251230013417.37393-1-dongtai.guo@linux.dev/

---
Changes in v7:
- Create patches based on loongarch-next branch(previously used master)
- Link to v6: https://lore.kernel.org/r/20251215-2-v6-0-09a486e8df99@linux.dev

Changes in v6:
- Put SCQ information in hwcap
- Link to v5: https://lore.kernel.org/r/20251212-2-v5-0-704b3af55f7d@linux.dev

Changes in v5:
- Reordered the patches
- Link to v4: https://lore.kernel.org/r/20251205-2-v4-0-e5ab932cf219@linux.dev

Changes in v4:
- Add SCQ support detection
- Add spinlock to emulate 128-bit cmpxchg
- Link to v3: https://lore.kernel.org/r/20251126-2-v3-0-851b5a516801@linux.dev

Changes in v3:
- dbar 0 -> __WEAK_LLSC_MB
- =ZB" (__ptr[0]) -> "r" (__ptr)
- Link to v2: https://lore.kernel.org/r/20251124-2-v2-0-b38216e25fd9@linux.dev

Changes in v2:
- Use a normal ld.d for the high word instead of ll.d to avoid race
  condition
- Insert a dbar between ll.d and ld.d to prevent reordering
- Simply __cmpxchg128_asm("ll.d", "sc.q", ptr, o, n) to __cmpxchg128_asm(ptr, o, n)
- Fix address operand constraints after testing different approaches:
  * ld.d with "m"
  * ll.d with "ZC",
  * sc.q with "ZB"(alternative constraints caused issues:
   - "r"  caused system hang
   - "ZC" caused compiler error:
     {standard input}: Assembler messages:
     {standard input}:10037: Fatal error: Immediate overflow.
     format: u0:0 )
- Link to v1: https://lore.kernel.org/r/20251120-2-v1-0-705bdc440550@linux.dev


George Guo (3):
  LoongArch: Add SCQ support detection
  LoongArch: Add 128-bit atomic cmpxchg support
  LoongArch: Replace seq_printf with seq_puts for simple strings

 arch/loongarch/Kconfig                    |  2 +
 arch/loongarch/include/asm/cmpxchg.h      | 48 +++++++++++++++++
 arch/loongarch/include/asm/cpu-features.h |  1 +
 arch/loongarch/include/asm/cpu.h          |  2 +
 arch/loongarch/include/uapi/asm/hwcap.h   |  1 +
 arch/loongarch/kernel/cpu-probe.c         |  4 ++
 arch/loongarch/kernel/proc.c              | 63 ++++++++++++++---------
 7 files changed, 98 insertions(+), 23 deletions(-)

-- 
2.49.0