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Message-ID: <19e3980b-043a-40bc-9944-3ff2ef389ab7@baylibre.com>
Date: Mon, 12 Jan 2026 11:10:22 -0600
From: David Lechner <dlechner@...libre.com>
To: Andy Shevchenko <andriy.shevchenko@...el.com>
Cc: Mark Brown <broonie@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Marcelo Schmitt <marcelo.schmitt@...log.com>,
Michael Hennerich <michael.hennerich@...log.com>,
Nuno Sá <nuno.sa@...log.com>,
Jonathan Cameron <jic23@...nel.org>, Andy Shevchenko <andy@...nel.org>,
Sean Anderson <sean.anderson@...ux.dev>, linux-spi@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-iio@...r.kernel.org
Subject: Re: [PATCH v4 4/9] spi: add multi_lane_mode field to struct
spi_transfer
On 12/27/25 9:14 AM, Andy Shevchenko wrote:
> On Fri, Dec 19, 2025 at 03:32:12PM -0600, David Lechner wrote:
>> Add a new multi_lane_mode field to struct spi_transfer to allow
>> peripherals that support multiple SPI lanes to be used with a single
>> SPI controller.
>>
>> This requires both the peripheral and the controller to have multiple
>> serializers connected to separate data lanes. It could also be used with
>> a single controller and multiple peripherals that are functioning as a
>> single logical device (similar to parallel memories).
>
> ...
>
>> unsigned cs_change:1;
>> unsigned tx_nbits:4;
>> unsigned rx_nbits:4;
>> +
>> +#define SPI_MULTI_LANE_MODE_SINGLE 0 /* only use single lane */
>> +#define SPI_MULTI_LANE_MODE_STRIPE 1 /* one data word per lane */
>> +#define SPI_MULTI_LANE_MODE_MIRROR 2 /* same word sent on all lanes */
>> + unsigned multi_lane_mode: 2;
>> +
>> unsigned timestamped:1;
>
> Btw, have you checked the layout of these bitfields? Are they all in one 32-bit
> word or split? Dunno if `pahole` handles them, never actually paid attention
> before.
>
There are only 14 bits used so far.
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