lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <3c434477.2d22.19bb0fd3f21.Coremail.lizhi2@eswincomputing.com>
Date: Mon, 12 Jan 2026 14:55:45 +0800 (GMT+08:00)
From: 李志 <lizhi2@...incomputing.com>
To: "Andrew Lunn" <andrew@...n.ch>
Cc: devicetree@...r.kernel.org, andrew+netdev@...n.ch, davem@...emloft.net,
	edumazet@...gle.com, kuba@...nel.org, robh@...nel.org,
	krzk+dt@...nel.org, conor+dt@...nel.org, netdev@...r.kernel.org,
	pabeni@...hat.com, mcoquelin.stm32@...il.com,
	alexandre.torgue@...s.st.com, rmk+kernel@...linux.org.uk,
	linux-stm32@...md-mailman.stormreply.com,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	ningyu@...incomputing.com, linmin@...incomputing.com,
	pinkesh.vaghela@...fochips.com, weishangjuan@...incomputing.com
Subject: Re: Re: [PATCH v1 2/2] net: stmmac: eic7700: enable clocks before
 syscon access and correct RX sampling timing




> -----原始邮件-----
> 发件人: "Andrew Lunn" <andrew@...n.ch>
> 发送时间:2026-01-10 02:31:09 (星期六)
> 收件人: lizhi2@...incomputing.com
> 抄送: devicetree@...r.kernel.org, andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, netdev@...r.kernel.org, pabeni@...hat.com, mcoquelin.stm32@...il.com, alexandre.torgue@...s.st.com, rmk+kernel@...linux.org.uk, linux-stm32@...md-mailman.stormreply.com, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, ningyu@...incomputing.com, linmin@...incomputing.com, pinkesh.vaghela@...fochips.com, weishangjuan@...incomputing.com
> 主题: Re: [PATCH v1 2/2] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing
> 
> > +	dwc_priv->eic7700_hsp_regmap =
> > +			syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> > +							"eswin,hsp-sp-csr");
> > +	if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
> >  		return dev_err_probe(&pdev->dev,
> > -				PTR_ERR(eic7700_hsp_regmap),
> > +				PTR_ERR(dwc_priv->eic7700_hsp_regmap),
> >  				"Failed to get hsp-sp-csr regmap\n");
> 
> In order to be backwards compatible, you cannot error out here,
> because old DT blobs won't have this property.
> 

Thanks for the review.

We would like to clarify our understanding before changing the behavior.

'eswin,hsp-sp-csr' has been documented as a required property since the
initial EIC7700 DWMAC binding, and the existing driver already relies on
it for RX/TX clock delay programming. From our understanding, this
property is fundamental to correct MAC clock configuration on EIC7700,
rather than an optional enhancement.

Given this, could you please clarify whether we should still treat
eswin,hsp-sp-csr as optional at runtime purely for DT ABI robustness,
even though it is required by the binding and hardware design?

Once confirmed, we will update the driver and binding accordingly.

Thanks,
Li Zhi

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ