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Message-ID: <2E7090A0C462255A+6658f83c-4e5b-4f49-a90b-54eecd61fcbf@radxa.com>
Date: Mon, 12 Jan 2026 15:25:05 +0800
From: Xilin Wu <sophon@...xa.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
 Rob Clark <robin.clark@....qualcomm.com>, Dmitry Baryshkov
 <lumag@...nel.org>, Abhinav Kumar <abhinav.kumar@...ux.dev>,
 Jessica Zhang <jesszhan0024@...il.com>, Sean Paul <sean@...rly.run>,
 Marijn Suijten <marijn.suijten@...ainline.org>,
 David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
 freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
 Jessica Zhang <jessica.zhang@....qualcomm.com>
Subject: Re: [PATCH v3 1/3] drm/msm/dpu: check mode against PINGPONG or DSC
 max width

On 1/12/2026 11:11 AM, Dmitry Baryshkov wrote:
> From: Jessica Zhang <jessica.zhang@....qualcomm.com>
> 
> LM block doesn't have a hardware buffer (unlike PINGPONG and DSC
> encoders). As such, don't use ephemeral max_mixer_width and
> MAX_HDISPLAY_SPLIT to validate requested modes. Instead use PP and DSC
> buffer widths.
> 
> While on the DPU 8.x+ supports a max linewidth of 8960 for PINGPONG_0,
> there is some additional logic that needs to be added to the resource
> manager to specifically try and reserve PINGPONG_0 for modes that are
> greater than 5k.
> 
> Signed-off-by: Jessica Zhang <jessica.zhang@....qualcomm.com>
> Tested-by: Xilin Wu <sophon@...xa.com> # qcs6490-radxa-dragon-q6a
> [DB: reworked to drop catalog changes, updated commit message]
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>

Sorry for the late reply, my colleagues are still testing the new series 
on qcs6490.

However, this completely breaks 4K 120Hz display on SC8280XP CRD, which 
was previously functional (albeit with the clock check bypassed [1]). 
The display now shows a solid blue screen. Kernel logs indicate that 
only one layer mixer is being used, instead of the two that were used 
previously.

[1] 
https://lore.kernel.org/all/F4CDF36128041430+0d030e3b-054c-4910-a132-72273c541948@radxa.com/

-- 
Best regards,
Xilin Wu <sophon@...xa.com>

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